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b47002ed65
[ Upstream commit 6db2526c1d694c91c6e05e2f186c085e9460f202 ] Setting and clearing CPU bits in the mm_cpumask is only ever done by the CPU itself, from the context switch code or the TLB flush code. Synchronization is handled by switch_mm_irqs_off() blocking interrupts. Sending TLB flush IPIs to CPUs that are in the mm_cpumask, but no longer running the program causes a regression in the will-it-scale tlbflush2 test. This test is contrived, but a large regression here might cause a small regression in some real world workload. Instead of always sending IPIs to CPUs that are in the mm_cpumask, but no longer running the program, send these IPIs only once a second. The rest of the time we can skip over CPUs where the loaded_mm is different from the target mm. Reported-by: kernel test roboto <oliver.sang@intel.com> Signed-off-by: Rik van Riel <riel@surriel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: https://lore.kernel.org/r/20241204210316.612ee573@fangorn Closes: https://lore.kernel.org/oe-lkp/202411282207.6bd28eae-lkp@intel.com/ Signed-off-by: Sasha Levin <sashal@kernel.org>
72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_MMU_H
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#define _ASM_X86_MMU_H
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#include <linux/spinlock.h>
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#include <linux/rwsem.h>
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#include <linux/mutex.h>
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#include <linux/atomic.h>
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#include <linux/bits.h>
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/* Uprobes on this MM assume 32-bit code */
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#define MM_CONTEXT_UPROBE_IA32 BIT(0)
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/* vsyscall page is accessible on this MM */
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#define MM_CONTEXT_HAS_VSYSCALL BIT(1)
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/*
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* x86 has arch-specific MMU state beyond what lives in mm_struct.
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*/
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typedef struct {
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/*
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* ctx_id uniquely identifies this mm_struct. A ctx_id will never
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* be reused, and zero is not a valid ctx_id.
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*/
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u64 ctx_id;
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/*
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* Any code that needs to do any sort of TLB flushing for this
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* mm will first make its changes to the page tables, then
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* increment tlb_gen, then flush. This lets the low-level
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* flushing code keep track of what needs flushing.
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*
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* This is not used on Xen PV.
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*/
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atomic64_t tlb_gen;
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unsigned long next_trim_cpumask;
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#ifdef CONFIG_MODIFY_LDT_SYSCALL
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struct rw_semaphore ldt_usr_sem;
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struct ldt_struct *ldt;
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#endif
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#ifdef CONFIG_X86_64
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unsigned short flags;
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#endif
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struct mutex lock;
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void __user *vdso; /* vdso base address */
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const struct vdso_image *vdso_image; /* vdso image in use */
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atomic_t perf_rdpmc_allowed; /* nonzero if rdpmc is allowed */
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#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
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/*
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* One bit per protection key says whether userspace can
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* use it or not. protected by mmap_lock.
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*/
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u16 pkey_allocation_map;
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s16 execute_only_pkey;
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#endif
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} mm_context_t;
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#define INIT_MM_CONTEXT(mm) \
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.context = { \
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.ctx_id = 1, \
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.lock = __MUTEX_INITIALIZER(mm.context.lock), \
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}
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void leave_mm(int cpu);
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#define leave_mm leave_mm
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#endif /* _ASM_X86_MMU_H */
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