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c150b809f7
* Support for various vector-accelerated crypto routines.
* Hibernation is now enabled for portable kernel builds.
* mmap_rnd_bits_max is larger on systems with larger VAs.
* Support for fast GUP.
* Support for membarrier-based instruction cache synchronization.
* Support for the Andes hart-level interrupt controller and PMU.
* Some cleanups around unaligned access speed probing and Kconfig
settings.
* Support for ACPI LPI and CPPC.
* Various cleanus related to barriers.
* A handful of fixes.
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Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
- Support for various vector-accelerated crypto routines
- Hibernation is now enabled for portable kernel builds
- mmap_rnd_bits_max is larger on systems with larger VAs
- Support for fast GUP
- Support for membarrier-based instruction cache synchronization
- Support for the Andes hart-level interrupt controller and PMU
- Some cleanups around unaligned access speed probing and Kconfig
settings
- Support for ACPI LPI and CPPC
- Various cleanus related to barriers
- A handful of fixes
* tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits)
riscv: Fix syscall wrapper for >word-size arguments
crypto: riscv - add vector crypto accelerated AES-CBC-CTS
crypto: riscv - parallelize AES-CBC decryption
riscv: Only flush the mm icache when setting an exec pte
riscv: Use kcalloc() instead of kzalloc()
riscv/barrier: Add missing space after ','
riscv/barrier: Consolidate fence definitions
riscv/barrier: Define RISCV_FULL_BARRIER
riscv/barrier: Define __{mb,rmb,wmb}
RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ
cpufreq: Move CPPC configs to common Kconfig and add RISC-V
ACPI: RISC-V: Add CPPC driver
ACPI: Enable ACPI_PROCESSOR for RISC-V
ACPI: RISC-V: Add LPI driver
cpuidle: RISC-V: Move few functions to arch/riscv
riscv: Introduce set_compat_task() in asm/compat.h
riscv: Introduce is_compat_thread() into compat.h
riscv: add compile-time test into is_compat_task()
riscv: Replace direct thread flag check with is_compat_task()
riscv: Improve arch_get_mmap_end() macro
...
63 lines
1.8 KiB
C
63 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2021 Western Digital Corporation or its affiliates.
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* Copyright (c) 2022 Ventana Micro Systems Inc.
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*/
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#ifndef _ASM_RISCV_SUSPEND_H
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#define _ASM_RISCV_SUSPEND_H
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#include <asm/ptrace.h>
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struct suspend_context {
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/* Saved and restored by low-level functions */
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struct pt_regs regs;
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/* Saved and restored by high-level functions */
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unsigned long scratch;
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unsigned long envcfg;
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unsigned long tvec;
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unsigned long ie;
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#ifdef CONFIG_MMU
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unsigned long satp;
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#endif
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};
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/*
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* Used by hibernation core and cleared during resume sequence
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*/
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extern int in_suspend;
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/* Low-level CPU suspend entry function */
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int __cpu_suspend_enter(struct suspend_context *context);
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/* High-level CPU suspend which will save context and call finish() */
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int cpu_suspend(unsigned long arg,
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int (*finish)(unsigned long arg,
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unsigned long entry,
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unsigned long context));
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/* Low-level CPU resume entry function */
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int __cpu_resume_enter(unsigned long hartid, unsigned long context);
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/* Used to save and restore the CSRs */
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void suspend_save_csrs(struct suspend_context *context);
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void suspend_restore_csrs(struct suspend_context *context);
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/* Low-level API to support hibernation */
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int swsusp_arch_suspend(void);
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int swsusp_arch_resume(void);
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int arch_hibernation_header_save(void *addr, unsigned int max_size);
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int arch_hibernation_header_restore(void *addr);
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int __hibernate_cpu_resume(void);
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/* Used to resume on the CPU we hibernated on */
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int hibernate_resume_nonboot_cpu_disable(void);
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asmlinkage void hibernate_restore_image(unsigned long resume_satp, unsigned long satp_temp,
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unsigned long cpu_resume);
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asmlinkage int hibernate_core_restore_code(void);
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bool riscv_sbi_hsm_is_supported(void);
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bool riscv_sbi_suspend_state_is_valid(u32 state);
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int riscv_sbi_hart_suspend(u32 state);
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#endif
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