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c5b15ddf11
By default, CMN has automatic clock-gating with the implication that a DTC's cycle counter may not increment while the DTC is sufficiently idle. Given that we may have up to 4 DTCs to choose from when scheduling a cycles event, this may potentially lead to surprising results if trying to measure metrics based on activity in a different DTC domain from where cycles end up being counted. Furthermore, since the details of internal clock gating are not documented, we can't even reason about what "active" cycles for a DTC actually mean relative to the activity of other nodes within the same nominal DTC domain. Make the reasonable assumption that if the user wants to count cycles, they almost certainly want to count all of the cycles, and disable clock gating while a DTC's cycle counter is in use. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Link: https://lore.kernel.org/r/c47cfdc09e907b1d7753d142a7e659982cceb246.1725296395.git.robin.murphy@arm.com Signed-off-by: Will Deacon <will@kernel.org> |
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| .. | ||
| amlogic | ||
| arm_cspmu | ||
| hisilicon | ||
| alibaba_uncore_drw_pmu.c | ||
| apple_m1_cpu_pmu.c | ||
| arm_dmc620_pmu.c | ||
| arm_dsu_pmu.c | ||
| arm_pmu_acpi.c | ||
| arm_pmu_platform.c | ||
| arm_pmu.c | ||
| arm_pmuv3.c | ||
| arm_smmuv3_pmu.c | ||
| arm_spe_pmu.c | ||
| arm_v6_pmu.c | ||
| arm_v7_pmu.c | ||
| arm_xscale_pmu.c | ||
| arm-cci.c | ||
| arm-ccn.c | ||
| arm-cmn.c | ||
| cxl_pmu.c | ||
| dwc_pcie_pmu.c | ||
| fsl_imx8_ddr_perf.c | ||
| fsl_imx9_ddr_perf.c | ||
| Kconfig | ||
| Makefile | ||
| marvell_cn10k_ddr_pmu.c | ||
| marvell_cn10k_tad_pmu.c | ||
| qcom_l2_pmu.c | ||
| qcom_l3_pmu.c | ||
| riscv_pmu_legacy.c | ||
| riscv_pmu_sbi.c | ||
| riscv_pmu.c | ||
| starfive_starlink_pmu.c | ||
| thunderx2_pmu.c | ||
| xgene_pmu.c | ||