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ae16f05c92
Introduce the advanced extended interrupt controllers (AVECINTC). This
feature will allow each core to have 256 independent interrupt vectors
and MSI interrupts can be independently routed to any vector on any CPU.
The whole topology of irqchips in LoongArch machines looks like this if
AVECINTC is supported:
+-----+ +-----------------------+ +-------+
| IPI | --> | CPUINTC | <-- | Timer |
+-----+ +-----------------------+ +-------+
^ ^ ^
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+---------+ +----------+ +---------+ +-------+
| EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
+---------+ +----------+ +---------+ +-------+
^ ^
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+---------+ +---------+
| PCH-PIC | | PCH-MSI |
+---------+ +---------+
^ ^ ^
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+---------+ +---------+ +---------+
| Devices | | PCH-LPC | | Devices |
+---------+ +---------+ +---------+
^
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+---------+
| Devices |
+---------+
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Co-developed-by: Liupu Wang <wangliupu@loongson.cn>
Signed-off-by: Liupu Wang <wangliupu@loongson.cn>
Co-developed-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20240823104337.25577-2-zhangtianyang@loongson.cn
133 lines
3.7 KiB
C
133 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_IRQ_H
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#define _ASM_IRQ_H
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#include <linux/irqdomain.h>
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#include <linux/irqreturn.h>
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#define IRQ_STACK_SIZE THREAD_SIZE
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#define IRQ_STACK_START (IRQ_STACK_SIZE - 16)
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DECLARE_PER_CPU(unsigned long, irq_stack);
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/*
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* The highest address on the IRQ stack contains a dummy frame which is
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* structured as follows:
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*
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* top ------------
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* | task sp | <- irq_stack[cpu] + IRQ_STACK_START
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* ------------
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* | | <- First frame of IRQ context
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* ------------
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*
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* task sp holds a copy of the task stack pointer where the struct pt_regs
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* from exception entry can be found.
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*/
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static inline bool on_irq_stack(int cpu, unsigned long sp)
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{
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unsigned long low = per_cpu(irq_stack, cpu);
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unsigned long high = low + IRQ_STACK_SIZE;
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return (low <= sp && sp <= high);
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}
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void spurious_interrupt(void);
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#define NR_IRQS_LEGACY 16
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/*
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* 256 Vectors Mapping for AVECINTC:
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*
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* 0 - 15: Mapping classic IPs, e.g. IP0-12.
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* 16 - 255: Mapping vectors for external IRQ.
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*
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*/
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#define NR_VECTORS 256
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#define NR_LEGACY_VECTORS 16
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#define IRQ_MATRIX_BITS NR_VECTORS
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#define arch_trigger_cpumask_backtrace arch_trigger_cpumask_backtrace
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void arch_trigger_cpumask_backtrace(const struct cpumask *mask, int exclude_cpu);
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#define MAX_IO_PICS 2
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#define NR_IRQS (64 + NR_VECTORS * (NR_CPUS + MAX_IO_PICS))
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struct acpi_vector_group {
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int node;
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int pci_segment;
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struct irq_domain *parent;
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};
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extern struct acpi_vector_group pch_group[MAX_IO_PICS];
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extern struct acpi_vector_group msi_group[MAX_IO_PICS];
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#define CORES_PER_EIO_NODE 4
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#define LOONGSON_CPU_UART0_VEC 10 /* CPU UART0 */
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#define LOONGSON_CPU_THSENS_VEC 14 /* CPU Thsens */
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#define LOONGSON_CPU_HT0_VEC 16 /* CPU HT0 irq vector base number */
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#define LOONGSON_CPU_HT1_VEC 24 /* CPU HT1 irq vector base number */
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/* IRQ number definitions */
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#define LOONGSON_LPC_IRQ_BASE 0
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#define LOONGSON_LPC_LAST_IRQ (LOONGSON_LPC_IRQ_BASE + 15)
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#define LOONGSON_CPU_IRQ_BASE 16
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#define LOONGSON_CPU_LAST_IRQ (LOONGSON_CPU_IRQ_BASE + 15)
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#define LOONGSON_PCH_IRQ_BASE 64
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#define LOONGSON_PCH_ACPI_IRQ (LOONGSON_PCH_IRQ_BASE + 47)
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#define LOONGSON_PCH_LAST_IRQ (LOONGSON_PCH_IRQ_BASE + 64 - 1)
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#define LOONGSON_MSI_IRQ_BASE (LOONGSON_PCH_IRQ_BASE + 64)
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#define LOONGSON_MSI_LAST_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1)
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#define GSI_MIN_LPC_IRQ LOONGSON_LPC_IRQ_BASE
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#define GSI_MAX_LPC_IRQ (LOONGSON_LPC_IRQ_BASE + 16 - 1)
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#define GSI_MIN_CPU_IRQ LOONGSON_CPU_IRQ_BASE
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#define GSI_MAX_CPU_IRQ (LOONGSON_CPU_IRQ_BASE + 48 - 1)
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#define GSI_MIN_PCH_IRQ LOONGSON_PCH_IRQ_BASE
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#define GSI_MAX_PCH_IRQ (LOONGSON_PCH_IRQ_BASE + 256 - 1)
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struct acpi_madt_lio_pic;
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struct acpi_madt_eio_pic;
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struct acpi_madt_ht_pic;
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struct acpi_madt_bio_pic;
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struct acpi_madt_msi_pic;
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struct acpi_madt_lpc_pic;
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void complete_irq_moving(void);
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struct fwnode_handle *get_pch_msi_handle(int pci_segment);
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extern struct acpi_madt_lio_pic *acpi_liointc;
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extern struct acpi_madt_eio_pic *acpi_eiointc[MAX_IO_PICS];
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extern struct acpi_madt_ht_pic *acpi_htintc;
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extern struct acpi_madt_lpc_pic *acpi_pchlpc;
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extern struct acpi_madt_msi_pic *acpi_pchmsi[MAX_IO_PICS];
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extern struct acpi_madt_bio_pic *acpi_pchpic[MAX_IO_PICS];
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extern struct fwnode_handle *cpuintc_handle;
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extern struct fwnode_handle *liointc_handle;
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extern struct fwnode_handle *pch_lpc_handle;
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extern struct fwnode_handle *pch_pic_handle[MAX_IO_PICS];
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static inline int get_percpu_irq(int vector)
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{
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struct irq_domain *d;
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d = irq_find_matching_fwnode(cpuintc_handle, DOMAIN_BUS_ANY);
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if (d)
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return irq_create_mapping(d, vector);
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return -EINVAL;
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}
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#include <asm-generic/irq.h>
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#endif /* _ASM_IRQ_H */
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