Shyam Sundar S K ced86959d2 i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold ... The current driver sets the response buffer threshold value to 1 (N+1, 2 DWORDS) in the QUEUE THRESHOLD register. However, the AMD I3C controller only generates interrupts when the response buffer threshold value is set to 0 (1 DWORD). Therefore, a quirk is added to set the response buffer threshold value to 0. Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Co-developed-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Signed-off-by: Krishnamoorthi M <krishnamoorthi.m@amd.com> Co-developed-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com> Signed-off-by: Guruvendra Punugupati <Guruvendra.Punugupati@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Link: https://lore.kernel.org/r/20240829091713.736217-7-Shyam-sundar.S-k@amd.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>		2024-09-05 18:34:09 +02:00
..
master	i3c: mipi-i3c-hci: Add a quirk to set Response buffer threshold	2024-09-05 18:34:09 +02:00
device.c	i3c: Add comment for -EAGAIN in i3c_device_do_priv_xfers()	2024-05-23 00:29:19 +02:00
internals.h	i3c: master: Enhance i3c_bus_type visibility for device searching & event monitoring	2024-07-26 14:21:30 +02:00
Kconfig
Makefile
master.c	I3C for 6.11	2024-07-27 10:53:06 -07:00