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eef6dcbc52
Extend the existing Tegra186 GPIO controller device tree bindings with support for the GPIO controller found on Tegra256. The number of pins is slightly different, but the programming model remains the same Add a new header, include/dt-bindings/gpio/tegra256-gpio.h, that defines port IDs as well as the TEGRA256_MAIN_GPIO() helper, both of which are used in conjunction to create a unique specifier for each pin. The OS can reconstruct the port ID and pin from these values to determine the register region for the corresponding GPIO. However, the OS does not use the macro definitions in this file. The symbolic names help associate these GPIO specifiers with the names used in the technical documentation available for the chip. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250823055420.24664-1-pshete@nvidia.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
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| .. | ||
| arm | ||
| ata | ||
| bus | ||
| clock | ||
| display | ||
| dma | ||
| firmware | ||
| gce | ||
| gpio | ||
| i2c | ||
| i3c | ||
| iio | ||
| input | ||
| interconnect | ||
| interrupt-controller | ||
| leds | ||
| mailbox | ||
| media | ||
| memory | ||
| mfd | ||
| mips | ||
| mux | ||
| net | ||
| nvmem | ||
| phy | ||
| pinctrl | ||
| pmu | ||
| power | ||
| pwm | ||
| regulator | ||
| reset | ||
| soc | ||
| sound | ||
| spmi | ||
| thermal | ||
| usb | ||
| watchdog | ||