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Register PCH_PIC_INT_ID constains version and supported irq number information, and it is a read only register. The detailed value can be set at initial stage, rather than read callback. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
76 lines
2.2 KiB
C
76 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2024 Loongson Technology Corporation Limited
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*/
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#ifndef __ASM_KVM_PCH_PIC_H
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#define __ASM_KVM_PCH_PIC_H
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#include <kvm/iodev.h>
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#define PCH_PIC_SIZE 0x3e8
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#define PCH_PIC_INT_ID_START 0x0
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#define PCH_PIC_INT_ID_END 0x7
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#define PCH_PIC_MASK_START 0x20
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#define PCH_PIC_MASK_END 0x27
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#define PCH_PIC_HTMSI_EN_START 0x40
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#define PCH_PIC_HTMSI_EN_END 0x47
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#define PCH_PIC_EDGE_START 0x60
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#define PCH_PIC_EDGE_END 0x67
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#define PCH_PIC_CLEAR_START 0x80
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#define PCH_PIC_CLEAR_END 0x87
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#define PCH_PIC_AUTO_CTRL0_START 0xc0
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#define PCH_PIC_AUTO_CTRL0_END 0xc7
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#define PCH_PIC_AUTO_CTRL1_START 0xe0
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#define PCH_PIC_AUTO_CTRL1_END 0xe7
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#define PCH_PIC_ROUTE_ENTRY_START 0x100
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#define PCH_PIC_ROUTE_ENTRY_END 0x13f
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#define PCH_PIC_HTMSI_VEC_START 0x200
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#define PCH_PIC_HTMSI_VEC_END 0x23f
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#define PCH_PIC_INT_IRR_START 0x380
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#define PCH_PIC_INT_IRR_END 0x38f
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#define PCH_PIC_INT_ISR_START 0x3a0
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#define PCH_PIC_INT_ISR_END 0x3af
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#define PCH_PIC_POLARITY_START 0x3e0
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#define PCH_PIC_POLARITY_END 0x3e7
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#define PCH_PIC_INT_ID_VAL 0x7UL
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#define PCH_PIC_INT_ID_VER 0x1UL
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union pch_pic_id {
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struct {
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uint8_t reserved_0[3];
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uint8_t id;
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uint8_t version;
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uint8_t reserved_1;
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uint8_t irq_num;
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uint8_t reserved_2;
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} desc;
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uint64_t data;
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};
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struct loongarch_pch_pic {
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spinlock_t lock;
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struct kvm *kvm;
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struct kvm_io_device device;
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union pch_pic_id id;
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uint64_t mask; /* 1:disable irq, 0:enable irq */
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uint64_t htmsi_en; /* 1:msi */
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uint64_t edge; /* 1:edge triggered, 0:level triggered */
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uint64_t auto_ctrl0; /* only use default value 00b */
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uint64_t auto_ctrl1; /* only use default value 00b */
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uint64_t last_intirr; /* edge detection */
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uint64_t irr; /* interrupt request register */
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uint64_t isr; /* interrupt service register */
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uint64_t polarity; /* 0: high level trigger, 1: low level trigger */
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uint8_t route_entry[64]; /* default value 0, route to int0: eiointc */
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uint8_t htmsi_vector[64]; /* irq route table for routing to eiointc */
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uint64_t pch_pic_base;
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};
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int kvm_loongarch_register_pch_pic_device(void);
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void pch_pic_set_irq(struct loongarch_pch_pic *s, int irq, int level);
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void pch_msi_set_irq(struct kvm *kvm, int irq, int level);
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#endif /* __ASM_KVM_PCH_PIC_H */
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