Lad Prabhakar 9549391bb6 clk: renesas: r9a07g043: Fix HP clock source for RZ/Five ... [ Upstream commit 7f22a298d9 ] According to the Rev.1.20 hardware manual for the RZ/Five SoC, the clock source for HP is derived from PLL6 divided by 2. Correct the implementation by configuring HP as a fixed clock source instead of a MUX. The `CPG_PL6_ETH_SSEL' register, which is available on the RZ/G2UL SoC, is not present on the RZ/Five SoC, necessitating this change. Fixes: 95d48d2703 ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Cc: stable@vger.kernel.org Reported-by: Hien Huynh <hien.huynh.px@renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250127173159.34572-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>		2025-05-02 07:50:40 +02:00
..
clk-div6.c
clk-div6.h
clk-emev2.c
clk-mstp.c
clk-r8a73a4.c
clk-r8a7740.c
clk-r8a7778.c
clk-r8a7779.c
clk-rz.c
clk-sh73a0.c
Kconfig
Makefile
r7s9210-cpg-mssr.c
r8a774a1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774b1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774c0-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a774e1-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a779a0-cpg-mssr.c	clk: renesas: r8a779a0: Fix CANFD parent clock	2024-06-12 11:12:08 +02:00
r8a779f0-cpg-mssr.c	clk: renesas: r8a779f0: Correct PFC/GPIO parent clock	2024-03-26 18:19:47 -04:00
r8a779g0-cpg-mssr.c	clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks	2024-03-26 18:19:47 -04:00
r8a7742-cpg-mssr.c
r8a7743-cpg-mssr.c
r8a7745-cpg-mssr.c
r8a7790-cpg-mssr.c
r8a7791-cpg-mssr.c
r8a7792-cpg-mssr.c
r8a7794-cpg-mssr.c
r8a7795-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a7796-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77470-cpg-mssr.c
r8a77965-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77970-cpg-mssr.c
r8a77980-cpg-mssr.c
r8a77990-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r8a77995-cpg-mssr.c	clk: renesas: rcar-gen3: Add ADG clocks	2023-08-15 11:34:43 +02:00
r9a06g032-clocks.c
r9a07g043-cpg.c	clk: renesas: r9a07g043: Fix HP clock source for RZ/Five	2025-05-02 07:50:40 +02:00
r9a07g044-cpg.c	clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable	2025-05-02 07:50:40 +02:00
r9a09g011-cpg.c
rcar-cpg-lib.c	clk: renesas: rcar-gen3: Extend SDnH divider table	2023-11-20 11:59:05 +01:00
rcar-cpg-lib.h
rcar-gen2-cpg.c
rcar-gen2-cpg.h
rcar-gen3-cpg.c
rcar-gen3-cpg.h
rcar-gen4-cpg.c
rcar-gen4-cpg.h
rcar-usb2-clock-sel.c
renesas-cpg-mssr.c
renesas-cpg-mssr.h
rzg2l-cpg.c	clk: renesas: rzg2l: Refactor SD mux driver	2025-05-02 07:50:40 +02:00
rzg2l-cpg.h	clk: renesas: rzg2l: Refactor SD mux driver	2025-05-02 07:50:40 +02:00