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[ Upstream commit391b06ecb6
] According to the i.MX93 Fusemap the two MAC addresses are stored in words 315 to 317 like this: 315 MAC1_ADDR_31_0[31:0] 316 MAC1_ADDR_47_32[47:32] MAC2_ADDR_15_0[15:0] 317 MAC2_ADDR_47_16[31:0] This means the MAC addresses are stored in reverse byte order. We have to swap the bytes before passing them to the upper layers. The storage format is consistent to the one used on i.MX6 using imx-ocotp driver which does the same byte swapping as introduced here. With this patch the MAC address on my i.MX93 TQ board correctly reads as 00:d0:93:6b:27:b8 instead of b8:27:6b:93:d0:00. Fixes:22e9e6fcfb
("nvmem: imx: support i.MX93 OCOTP") Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: stable <stable@kernel.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20241230141901.263976-4-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
200 lines
4.3 KiB
C
200 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* i.MX9 OCOTP fusebox driver
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*
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* Copyright 2023 NXP
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*/
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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enum fuse_type {
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FUSE_FSB = 1,
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FUSE_ELE = 2,
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FUSE_INVALID = -1
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};
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struct ocotp_map_entry {
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u32 start; /* start word */
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u32 num; /* num words */
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enum fuse_type type;
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};
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struct ocotp_devtype_data {
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u32 reg_off;
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char *name;
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u32 size;
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u32 num_entry;
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u32 flag;
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nvmem_reg_read_t reg_read;
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struct ocotp_map_entry entry[];
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};
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struct imx_ocotp_priv {
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struct device *dev;
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void __iomem *base;
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struct nvmem_config config;
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struct mutex lock;
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const struct ocotp_devtype_data *data;
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};
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static enum fuse_type imx_ocotp_fuse_type(void *context, u32 index)
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{
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struct imx_ocotp_priv *priv = context;
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const struct ocotp_devtype_data *data = priv->data;
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u32 start, end;
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int i;
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for (i = 0; i < data->num_entry; i++) {
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start = data->entry[i].start;
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end = data->entry[i].start + data->entry[i].num;
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if (index >= start && index < end)
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return data->entry[i].type;
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}
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return FUSE_INVALID;
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}
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static int imx_ocotp_reg_read(void *context, unsigned int offset, void *val, size_t bytes)
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{
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struct imx_ocotp_priv *priv = context;
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void __iomem *reg = priv->base + priv->data->reg_off;
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u32 count, index, num_bytes;
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enum fuse_type type;
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u32 *buf;
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void *p;
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int i;
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u8 skipbytes;
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if (offset + bytes > priv->data->size)
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bytes = priv->data->size - offset;
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index = offset >> 2;
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skipbytes = offset - (index << 2);
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num_bytes = round_up(bytes + skipbytes, 4);
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count = num_bytes >> 2;
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p = kzalloc(num_bytes, GFP_KERNEL);
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if (!p)
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return -ENOMEM;
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mutex_lock(&priv->lock);
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buf = p;
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for (i = index; i < (index + count); i++) {
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type = imx_ocotp_fuse_type(context, i);
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if (type == FUSE_INVALID || type == FUSE_ELE) {
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*buf++ = 0;
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continue;
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}
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*buf++ = readl_relaxed(reg + (i << 2));
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}
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memcpy(val, ((u8 *)p) + skipbytes, bytes);
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mutex_unlock(&priv->lock);
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kfree(p);
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return 0;
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};
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static int imx_ocotp_cell_pp(void *context, const char *id, int index,
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unsigned int offset, void *data, size_t bytes)
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{
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u8 *buf = data;
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int i;
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/* Deal with some post processing of nvmem cell data */
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if (id && !strcmp(id, "mac-address"))
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for (i = 0; i < bytes / 2; i++)
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swap(buf[i], buf[bytes - i - 1]);
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return 0;
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}
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static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem,
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struct nvmem_cell_info *cell)
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{
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cell->read_post_process = imx_ocotp_cell_pp;
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}
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static int imx_ele_ocotp_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct imx_ocotp_priv *priv;
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struct nvmem_device *nvmem;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->data = of_device_get_match_data(dev);
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priv->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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priv->config.dev = dev;
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priv->config.name = "ELE-OCOTP";
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priv->config.id = NVMEM_DEVID_AUTO;
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priv->config.owner = THIS_MODULE;
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priv->config.size = priv->data->size;
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priv->config.reg_read = priv->data->reg_read;
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priv->config.word_size = 1;
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priv->config.stride = 1;
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priv->config.priv = priv;
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priv->config.read_only = true;
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priv->config.add_legacy_fixed_of_cells = true;
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priv->config.fixup_dt_cell_info = imx_ocotp_fixup_dt_cell_info;
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mutex_init(&priv->lock);
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nvmem = devm_nvmem_register(dev, &priv->config);
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if (IS_ERR(nvmem))
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return PTR_ERR(nvmem);
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return 0;
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}
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static const struct ocotp_devtype_data imx93_ocotp_data = {
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.reg_off = 0x8000,
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.reg_read = imx_ocotp_reg_read,
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.size = 2048,
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.num_entry = 6,
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.entry = {
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{ 0, 52, FUSE_FSB },
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{ 63, 1, FUSE_ELE},
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{ 128, 16, FUSE_ELE },
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{ 182, 1, FUSE_ELE },
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{ 188, 1, FUSE_ELE },
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{ 312, 200, FUSE_FSB }
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},
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};
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static const struct of_device_id imx_ele_ocotp_dt_ids[] = {
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{ .compatible = "fsl,imx93-ocotp", .data = &imx93_ocotp_data, },
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{},
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};
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MODULE_DEVICE_TABLE(of, imx_ele_ocotp_dt_ids);
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static struct platform_driver imx_ele_ocotp_driver = {
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.driver = {
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.name = "imx_ele_ocotp",
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.of_match_table = imx_ele_ocotp_dt_ids,
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},
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.probe = imx_ele_ocotp_probe,
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};
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module_platform_driver(imx_ele_ocotp_driver);
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MODULE_DESCRIPTION("i.MX OCOTP/ELE driver");
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MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
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MODULE_LICENSE("GPL");
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