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u-boot-ge: Remove old u-boot recipe

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u-boot-ge was used by imx6q-elo board. The imxq-elo board has been
renamed to imx6q-dms-ba16 and now uses u-boot-fslc. Hence remove
old u-boot-ge recipe.

Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
This commit is contained in:
Akshay Bhat 2016-08-08 17:22:47 -04:00 committed by Otavio Salvador
parent 403262c0c9
commit 3dfb82fc7e
8 changed files with 0 additions and 2349 deletions
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1245
recipes-bsp/u-boot/u-boot-ge-2015.10/0001-arm-imx-Add-support-for-GE-Bx50v3-boards.patch
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293
recipes-bsp/u-boot/u-boot-ge-2015.10/0002-board-ge-bx50v3-Update-display-setup.patch
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@ -1,293 +0,0 @@
From 047844511f92e9e9ea089f019318280cb4c3a75a Mon Sep 17 00:00:00 2001
From: Akshay Bhat <akshay.bhat@timesys.com>
Date: Thu, 4 Feb 2016 12:22:52 -0500
Subject: [PATCH 2/7] board: ge: bx50v3: Update display setup
- Disable LVDS1 on B450v3/B650v3 boards since they no longer have
connectors for it.
- Implement imx6 MLK-10782-3 or ERR009219 errata for LVDS clock switch.
This patch was ported from Freescale 3.10.17_1.0.0_ga kernel to u-boot.
- Split the display setup into 2 different functions. One for B850v3 that
does a setup of LVDS and HDMI with clock source for LVDS/IPU_DI set to
video PLL. The other for B450v3/B650v3 that does a setup of LVDS only with
clock source for LVDS/IPU_DI set to USB PLL.
Upstream-Status: Pending
Waiting on v2 patch to get accepted.
http://lists.denx.de/pipermail/u-boot/2016-January/243985.html
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
---
board/ge/bx50v3/bx50v3.c | 240 ++++++++++++++++++++++++++++++++++++++---------
1 file changed, 198 insertions(+), 42 deletions(-)
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 70c298d..cf2cd1a 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -390,55 +390,208 @@ struct display_info_t const displays[] = {{
} } };
size_t display_count = ARRAY_SIZE(displays);
-static void setup_display(void)
+static void enable_videopll(void)
+{
+ struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ s32 timeout = 100000;
+
+ setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+ /* set video pll to 910MHz (24MHz * (37+11/12))
+ * video pll post div to 910/4 = 227.5MHz
+ */
+ clrsetbits_le32(&ccm->analog_pll_video,
+ BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+ BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
+
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+ clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+ while (timeout--)
+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+ break;
+ if (timeout < 0)
+ printf("Warning: video pll lock timeout!\n");
+
+ clrsetbits_le32(&ccm->analog_pll_video,
+ BM_ANADIG_PLL_VIDEO_BYPASS,
+ BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
+static void set_ldb_clock_source(u8 source)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
int reg;
+ /*
+ * Need to follow a strict procedure when changing the LDB
+ * clock, else we can introduce a glitch. Things to keep in
+ * mind:
+ * 1. The current and new parent clocks must be disabled.
+ * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has
+ * no CG bit.
+ * 3. In the RTL implementation of the LDB_DI_CLK_SEL mux
+ * the top four options are in one mux and the PLL3 option along
+ * with another option is in the second mux. There is third mux
+ * used to decide between the first and second mux.
+ * The code below switches the parent to the bottom mux first
+ * and then manipulates the top mux. This ensures that no glitch
+ * will enter the divider.
+ *
+ * Need to disable MMDC_CH1 clock manually as there is no CG bit
+ * for this clock. The only way to disable this clock is to move
+ * it to pll3_sw_clk and then to disable pll3_sw_clk
+ * Make sure periph2_clk2_sel is set to pll3_sw_clk
+ */
+ /* Set MMDC_CH1 mask bit */
+ reg = readl(&mxc_ccm->ccdr);
+ reg |= MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
+ writel(reg, &mxc_ccm->ccdr);
+
+ /* Set periph2_clk2_sel to be sourced from PLL3_sw_clk */
+ reg = readl(&mxc_ccm->cbcmr);
+ reg &= ~MXC_CCM_CBCMR_PERIPH2_CLK2_SEL;
+ writel(reg, &mxc_ccm->cbcmr);
+
+ /*
+ * Set the periph2_clk_sel to the top mux so that
+ * mmdc_ch1 is from pll3_sw_clk.
+ */
+ reg = readl(&mxc_ccm->cbcdr);
+ reg |= MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+ writel(reg, &mxc_ccm->cbcdr);
+
+ /* Wait for the clock switch */
+ while (readl(&mxc_ccm->cdhipr))
+ ;
+ /* Disable pll3_sw_clk by selecting bypass clock source */
+ reg = readl(&mxc_ccm->ccsr);
+ reg |= MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
+ writel(reg, &mxc_ccm->ccsr);
+
+ /* Set the ldb_di0_clk and ldb_di1_clk to 111b */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg |= ((7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+ | (7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+ writel(reg, &mxc_ccm->cs2cdr);
- enable_ipu_clock();
- imx_setup_hdmi();
-
- reg = readl(&mxc_ccm->CCGR3);
- reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
- writel(reg, &mxc_ccm->CCGR3);
+ /* Set the ldb_di0_clk and ldb_di1_clk to 100b */
+ reg = readl(&mxc_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
+ | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
+ reg |= ((4 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+ | (4 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
+ writel(reg, &mxc_ccm->cs2cdr);
+ /* Set the ldb_di0_clk and ldb_di1_clk to desired source */
reg = readl(&mxc_ccm->cs2cdr);
- reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
- MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
- reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
- (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
+ reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK
+ | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK);
+ reg |= ((source << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
+ | (source << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
writel(reg, &mxc_ccm->cs2cdr);
- reg = readl(&mxc_ccm->cscmr2);
- reg |= (MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
- writel(reg, &mxc_ccm->cscmr2);
-
- reg = readl(&mxc_ccm->chsccdr);
- reg |= (CHSCCDR_CLK_SEL_LDB_DI0
- << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
- writel(reg, &mxc_ccm->chsccdr);
-
- reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
- | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
- | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
- | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
- | IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT
- | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
- | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
- | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0
- | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
- writel(reg, &iomux->gpr[2]);
-
- reg = readl(&iomux->gpr[3]);
- reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
- IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
- IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
- << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
- | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
- << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
- writel(reg, &iomux->gpr[3]);
+ /* Unbypass pll3_sw_clk */
+ reg = readl(&mxc_ccm->ccsr);
+ reg &= ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL;
+ writel(reg, &mxc_ccm->ccsr);
+
+ /*
+ * Set the periph2_clk_sel back to the bottom mux so that
+ * mmdc_ch1 is from its original parent.
+ */
+ reg = readl(&mxc_ccm->cbcdr);
+ reg &= ~MXC_CCM_CBCDR_PERIPH2_CLK_SEL;
+ writel(reg, &mxc_ccm->cbcdr);
+
+ /* Wait for the clock switch */
+ while (readl(&mxc_ccm->cdhipr))
+ ;
+ /* Clear MMDC_CH1 mask bit */
+ reg = readl(&mxc_ccm->ccdr);
+ reg &= ~MXC_CCM_CCDR_MMDC_CH1_HS_MASK;
+ writel(reg, &mxc_ccm->ccdr);
+}
+
+static void setup_display_b850v3(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* Set LDB clock to Video PLL */
+ set_ldb_clock_source(0);
+ enable_videopll();
+
+ /* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
+ clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+ imx_setup_hdmi();
+
+ /* Set LDB_DI0 as clock source for IPU_DI0 */
+ clrsetbits_le32(&mxc_ccm->chsccdr,
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+ (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+ /* Turn on IPU LDB DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+ enable_ipu_clock();
+
+ writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+ IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+ IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+ IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
+ &iomux->gpr[2]);
+
+ clrbits_le32(&iomux->gpr[3],
+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
+}
+
+static void setup_display_bx50v3(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ /* Set LDB clock to USB PLL */
+ set_ldb_clock_source(4);
+
+ /* IPU1 DI0 clock is 480/7 = 68.5 MHz */
+ setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+ /* Set LDB_DI0 as clock source for IPU_DI0 */
+ clrsetbits_le32(&mxc_ccm->chsccdr,
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+ (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+ /* Turn on IPU LDB DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+ enable_ipu_clock();
+
+ writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
+ &iomux->gpr[2]);
+
+ clrsetbits_le32(&iomux->gpr[3],
+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
/* backlights off until needed */
imx_iomux_v3_setup_multiple_pads(backlight_pads,
@@ -487,7 +640,10 @@ int board_init(void)
gpio_direction_output(SUS_S3_OUT, 1);
gpio_direction_output(WIFI_EN, 1);
#if defined(CONFIG_VIDEO_IPUV3)
- setup_display();
+ if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+ setup_display_b850v3();
+ else
+ setup_display_bx50v3();
#endif
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
--
2.5.0

128
recipes-bsp/u-boot/u-boot-ge-2015.10/0003-ge_bx50v3-Add-support-for-FSL-Community-Yocto-images.patch
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@ -1,128 +0,0 @@
From 6b0a4665c760d25362752cc57ee239bb19e4f87d Mon Sep 17 00:00:00 2001
From: Justin Waters <justin.waters@timesys.com>
Date: Wed, 9 Mar 2016 13:16:39 -0500
Subject: [PATCH 3/7] ge_bx50v3: Add support for FSL Community Yocto images
The Freescale community images use two partitions: one for
boot files, the other for the RFS. This option makes the default
configurable at build time.
Signed-off-by: Justin Waters <justin.waters@timesys.com>
---
board/ge/bx50v3/Kconfig | 4 ++++
include/configs/ge_bx50v3.h | 36 ++++++++++++++++++++++++------------
2 files changed, 28 insertions(+), 12 deletions(-)
diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig
index d50dece..320b3b8 100644
--- a/board/ge/bx50v3/Kconfig
+++ b/board/ge/bx50v3/Kconfig
@@ -15,4 +15,8 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ge_bx50v3"
+config YOCTO_IMAGE
+ bool "Use yocto image layout"
+ default n
+
endif
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 6fa4a9a..4b3c25e 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -17,21 +17,31 @@
#if defined(CONFIG_TARGET_GE_B450V3)
#define CONFIG_BOARD_NAME "General Electric B450v3"
-#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b450v3.dtb"
+#define CONFIG_DEFAULT_FDT_FILE "imx6q-b450v3.dtb"
#elif defined(CONFIG_TARGET_GE_B650V3)
#define CONFIG_BOARD_NAME "General Electric B650v3"
-#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b650v3.dtb"
+#define CONFIG_DEFAULT_FDT_FILE "imx6q-b650v3.dtb"
#elif defined(CONFIG_TARGET_GE_B850V3)
#define CONFIG_BOARD_NAME "General Electric B850v3"
-#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b850v3.dtb"
+#define CONFIG_DEFAULT_FDT_FILE "mx6q-b850v3.dtb"
#else
#define CONFIG_BOARD_NAME "General Electric BA16 Generic"
-#define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-ba16.dtb"
+#define CONFIG_DEFAULT_FDT_FILE "imx6q-ba16.dtb"
#endif
#define CONFIG_MXC_UART_BASE UART3_BASE
#define CONFIG_CONSOLE_DEV "ttymxc2"
+#ifdef CONFIG_YOCTO_IMAGE
+#define CONFIG_BOOT_DIR ""
+#define CONFIG_LOADCMD "fatload"
+#define CONFIG_RFSPART "2"
+#else
+#define CONFIG_BOOT_DIR "/boot"
+#define CONFIG_LOADCMD "ext2load"
+#define CONFIG_RFSPART "1"
+#endif
+
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
#define CONFIG_SUPPORT_EMMC_BOOT
@@ -144,9 +154,9 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
- "image=/boot/uImage\0" \
+ "image=" CONFIG_BOOT_DIR "/uImage\0" \
"uboot=u-boot.imx\0" \
- "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \
"fdt_addr=0x18000000\0" \
"boot_fdt=yes\0" \
"ip_dyn=yes\0" \
@@ -156,6 +166,8 @@
"sddev=0\0" \
"emmcdev=1\0" \
"partnum=1\0" \
+ "loadcmd=" CONFIG_LOADCMD "\0" \
+ "rfspart=" CONFIG_RFSPART "\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
@@ -179,12 +191,12 @@
"setargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/${rootdev} rw rootwait cma=128M\0" \
"loadbootscript=" \
- "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
+ "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
" source\0" \
"loadimage=" \
- "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
- "loadfdt=ext2load ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
+ "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \
+ "loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \
"tryboot=" \
"if run loadbootscript; then " \
"run bootscript; " \
@@ -237,16 +249,16 @@
"usb start; " \
"setenv dev usb; " \
"setenv devnum 0; " \
- "setenv rootdev sda1; " \
+ "setenv rootdev sda${rfspart}; " \
"run tryboot; " \
\
"setenv dev mmc; " \
- "setenv rootdev mmcblk0p1; " \
+ "setenv rootdev mmcblk0p${rfspart}; " \
\
"setenv devnum ${sddev}; " \
"if mmc dev ${devnum}; then " \
"run tryboot; " \
- "setenv rootdev mmcblk1p1; " \
+ "setenv rootdev mmcblk1p${rfspart}; " \
"fi; " \
\
"setenv devnum ${emmcdev}; " \
--
2.5.0

222
recipes-bsp/u-boot/u-boot-ge-2015.10/0004-board-ge-bx50v3-Add-support-for-ELO-board.patch
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@ -1,222 +0,0 @@
From 51606911d456bbcbdb85337a87dd35ce059bed4f Mon Sep 17 00:00:00 2001
From: Justin Waters <justin.waters@timesys.com>
Date: Wed, 9 Mar 2016 13:19:14 -0500
Subject: [PATCH 4/7] board: ge: bx50v3: Add support for ELO board
The ELO board uses the same Q7 module as the bx50v3 boards, but with
a different baseboard. However, there are only two main differences
that affect U-boot:
1) Dual channel LVDS display
2) Serial console
Signed-off-by: Justin Waters <justin.waters@timesys.com>
---
arch/arm/cpu/armv7/mx6/Kconfig | 4 +++
board/ge/bx50v3/Kconfig | 2 +-
board/ge/bx50v3/bx50v3.c | 76 ++++++++++++++++++++++++++++++++++++++++++
configs/ge_elo_defconfig | 8 +++++
configs/ge_elo_yocto_defconfig | 9 +++++
include/configs/ge_bx50v3.h | 8 +++++
6 files changed, 106 insertions(+), 1 deletion(-)
create mode 100644 configs/ge_elo_defconfig
create mode 100644 configs/ge_elo_yocto_defconfig
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 722e0d0..b93c661 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -60,6 +60,10 @@ config TARGET_CM_FX6
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
+config TARGET_GE_ELO
+ bool "General Electric ELO"
+ select MX6Q
+
config TARGET_GE_B450V3
bool "General Electric B450v3"
select MX6Q
diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig
index 320b3b8..c88058b 100644
--- a/board/ge/bx50v3/Kconfig
+++ b/board/ge/bx50v3/Kconfig
@@ -1,4 +1,4 @@
-if TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
+if TARGET_GE_ELO || TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
config IMX_CONFIG
default "board/ge/bx50v3/bx50v3.cfg"
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index cf2cd1a..8d3e47a 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -324,6 +324,8 @@ static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight enable for LVDS display */
MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
+ /* Set PWM to GPIO so backlight is full strength */
+ MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void do_enable_hdmi(struct display_info_t const *dev)
@@ -344,6 +346,9 @@ static int detect_baseboard(struct display_info_t const *dev)
IS_ENABLED(CONFIG_TARGET_GE_B650V3))
return 1;
+ if (IS_ENABLED(CONFIG_TARGET_GE_ELO))
+ return (0 == dev->addr);
+
return 0;
}
@@ -369,6 +374,26 @@ struct display_info_t const displays[] = {{
.vmode = FB_VMODE_NONINTERLACED
} }, {
.bus = -1,
+ .addr = 0,
+ .pixfmt = IPU_PIX_FMT_RGB24,
+ .detect = detect_baseboard,
+ .enable = NULL,
+ .mode = {
+ .name = "SHARP-LQ156M1LG21",
+ .refresh = 60,
+ .xres = 1920,
+ .yres = 1080,
+ .pixclock = 7851,
+ .left_margin = 100,
+ .right_margin = 40,
+ .upper_margin = 30,
+ .lower_margin = 3,
+ .hsync_len = 10,
+ .vsync_len = 2,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+} }, {
+ .bus = -1,
.addr = 3,
.pixfmt = IPU_PIX_FMT_RGB24,
.detect = detect_hdmi,
@@ -559,6 +584,55 @@ static void setup_display_b850v3(void)
IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
}
+static void setup_display_elo(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+ set_ldb_clock_source(1);
+
+ clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
+
+ imx_setup_hdmi();
+
+ /* Set LDB_DI0 as clock source for IPU_DI0 */
+ clrsetbits_le32(&mxc_ccm->chsccdr,
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
+ (CHSCCDR_CLK_SEL_LDB_DI0 <<
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
+
+ /* Turn on IPU LDB DI0 clocks */
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
+
+ enable_ipu_clock();
+
+ writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
+ IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
+ IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
+ IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
+ IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
+ IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
+ IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
+ IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
+ IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
+ &iomux->gpr[2]);
+
+ clrsetbits_le32(&iomux->gpr[3],
+ IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
+ IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
+ IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
+ (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
+ IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
+
+ /* backlights off until needed */
+ imx_iomux_v3_setup_multiple_pads(backlight_pads,
+ ARRAY_SIZE(backlight_pads));
+
+ gpio_direction_input(LVDS_POWER_GP);
+ gpio_direction_input(LVDS_BACKLIGHT_GP);
+}
+
static void setup_display_bx50v3(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -642,6 +716,8 @@ int board_init(void)
#if defined(CONFIG_VIDEO_IPUV3)
if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
setup_display_b850v3();
+ else if (IS_ENABLED(CONFIG_TARGET_GE_ELO))
+ setup_display_elo();
else
setup_display_bx50v3();
#endif
diff --git a/configs/ge_elo_defconfig b/configs/ge_elo_defconfig
new file mode 100644
index 0000000..51835ce
--- /dev/null
+++ b/configs/ge_elo_defconfig
@@ -0,0 +1,8 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_GE_ELO=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
diff --git a/configs/ge_elo_yocto_defconfig b/configs/ge_elo_yocto_defconfig
new file mode 100644
index 0000000..1cd475c
--- /dev/null
+++ b/configs/ge_elo_yocto_defconfig
@@ -0,0 +1,9 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_GE_ELO=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_YOCTO_IMAGE=y
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 4b3c25e..8be4350 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -24,13 +24,21 @@
#elif defined(CONFIG_TARGET_GE_B850V3)
#define CONFIG_BOARD_NAME "General Electric B850v3"
#define CONFIG_DEFAULT_FDT_FILE "mx6q-b850v3.dtb"
+#elif defined(CONFIG_TARGET_GE_ELO)
+#define CONFIG_BOARD_NAME "General Electric ELO"
+#define CONFIG_DEFAULT_FDT_FILE "imx6q-elo.dtb"
#else
#define CONFIG_BOARD_NAME "General Electric BA16 Generic"
#define CONFIG_DEFAULT_FDT_FILE "imx6q-ba16.dtb"
#endif
+#if defined(CONFIG_TARGET_GE_ELO)
+#define CONFIG_MXC_UART_BASE UART4_BASE
+#define CONFIG_CONSOLE_DEV "ttymxc3"
+#else
#define CONFIG_MXC_UART_BASE UART3_BASE
#define CONFIG_CONSOLE_DEV "ttymxc2"
+#endif
#ifdef CONFIG_YOCTO_IMAGE
#define CONFIG_BOOT_DIR ""
--
2.5.0

37
recipes-bsp/u-boot/u-boot-ge-2015.10/0005-board-ge-bx50v3-Fix-bootargs-for-ELO-board.patch
View File

@ -1,37 +0,0 @@
From 17d0da9815466516a8daae8e6d5c6d797caa75fc Mon Sep 17 00:00:00 2001
From: Justin Waters <justin.waters@timesys.com>
Date: Thu, 10 Mar 2016 15:26:30 -0500
Subject: [PATCH 5/7] board: ge: bx50v3: Fix bootargs for ELO board
---
include/configs/ge_bx50v3.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 8be4350..5219746 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -35,9 +35,11 @@
#if defined(CONFIG_TARGET_GE_ELO)
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONFIG_CONSOLE_DEV "ttymxc3"
+#define CONFIG_EXTRA_BOOTARGS "panic=10"
#else
#define CONFIG_MXC_UART_BASE UART3_BASE
#define CONFIG_CONSOLE_DEV "ttymxc2"
+#define CONFIG_EXTRA_BOOTARGS "cma=128M"
#endif
#ifdef CONFIG_YOCTO_IMAGE
@@ -197,7 +199,7 @@
"echo 'U-Boot upgraded. Please reset'; " \
"fi\0" \
"setargs=setenv bootargs console=${console},${baudrate} " \
- "root=/dev/${rootdev} rw rootwait cma=128M\0" \
+ "root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \
"loadbootscript=" \
"${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \
--
2.5.0

343
recipes-bsp/u-boot/u-boot-ge-2015.10/0006-mx6q_ba16-Add-1G-DDR-support.patch
View File

@ -1,343 +0,0 @@
From 4fe4dc9cab80b3d61df30cb883081a3189b6660a Mon Sep 17 00:00:00 2001
From: Ken Lin <ken.lin@advantech.com.tw>
Date: Thu, 31 Mar 2016 12:45:11 +0800
Subject: [PATCH 6/7] mx6q_ba16: Add 1G DDR support
---
board/ge/bx50v3/Kconfig | 15 ++-
board/ge/bx50v3/ddr_1g.cfg | 262 ++++++++++++++++++++++++++++++++++++++
configs/ge_elo_yocto_1g_defconfig | 10 ++
include/configs/ge_bx50v3.h | 4 +
4 files changed, 290 insertions(+), 1 deletion(-)
create mode 100644 board/ge/bx50v3/ddr_1g.cfg
create mode 100644 configs/ge_elo_yocto_1g_defconfig
diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig
index c88058b..05cc07a 100644
--- a/board/ge/bx50v3/Kconfig
+++ b/board/ge/bx50v3/Kconfig
@@ -1,7 +1,20 @@
if TARGET_GE_ELO || TARGET_GE_B450V3 || TARGET_GE_B650V3 || TARGET_GE_B850V3
+choice
+ prompt "DDR Size"
+ default SYS_DDR_2G
+
+config SYS_DDR_1G
+ bool "1GiB"
+
+config SYS_DDR_2G
+ bool "2GiB"
+
+endchoice
+
config IMX_CONFIG
- default "board/ge/bx50v3/bx50v3.cfg"
+ default "board/ge/bx50v3/bx50v3.cfg" if SYS_DDR_2G
+ default "board/ge/bx50v3/ddr_1g.cfg" if SYS_DDR_1G
config SYS_BOARD
default "bx50v3"
diff --git a/board/ge/bx50v3/ddr_1g.cfg b/board/ge/bx50v3/ddr_1g.cfg
new file mode 100644
index 0000000..967082d
--- /dev/null
+++ b/board/ge/bx50v3/ddr_1g.cfg
@@ -0,0 +1,262 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+//*================================================================================================
+// Disable WDOG
+//*================================================================================================
+//setmem /16 0x020bc000 = 0x30
+
+
+//*================================================================================================
+// Enable all clocks (they are disabled by ROM code)
+//*================================================================================================
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+
+//*
+// Initialize 64-bit DDR3
+//*
+
+//######################################################
+// IOMUX
+//######################################################
+
+//DDR IO TYPE:
+DATA 4 0x020e0798 0x000c0000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE - DDR_SEL11
+DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE - PKE0 , Pull disabled for all, except DQS.
+
+//CLOCK:
+DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 - DSE101, DDR_INPUT0, HYS0
+DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 - DSE101, DDR_INPUT0, HYS0
+
+//ADDRESS:
+DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS - DSE110, DDR_INPUT1, HYS0
+DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS - DSE110, DDR_INPUT1, HYS0
+DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS - DSE110
+
+//CONTROL:
+DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET - DSE110, DDR_INPUT1, HYS0, DDR_SEL00
+
+DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
+DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0
+DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1
+DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS - DSE110
+
+
+//DATA STROBE:
+DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT1
+
+DATA 4 0x020e05a8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 - DSE110
+DATA 4 0x020e05b0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 - DSE110
+DATA 4 0x020e0524 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 - DSE110
+DATA 4 0x020e051c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 - DSE110
+DATA 4 0x020e0518 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 - DSE110
+DATA 4 0x020e050c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 - DSE110
+DATA 4 0x020e05b8 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 - DSE110
+DATA 4 0x020e05c0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 - DSE110
+
+//DATA:
+DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE- DDR_INPUT 1,diff
+
+DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS - DSE110
+DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS - DSE110
+DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS - DSE110
+DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS - DSE110
+DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS - DSE110
+DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS - DSE110
+DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS - DSE110
+DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS - DSE110
+
+DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 - DSE110, DDR_INPUT1, HYS0
+DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 - DSE110, DDR_INPUT1, HYS0
+DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 - DSE110, DDR_INPUT1, HYS0
+DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 - DSE110, DDR_INPUT1, HYS0
+DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 - DSE110, DDR_INPUT1, HYS0
+DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 - DSE110, DDR_INPUT1, HYS0
+DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 - DSE110, DDR_INPUT1, HYS0
+DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 - DSE110, DDR_INPUT1, HYS0
+
+
+
+//######################################################
+//Calibrations:
+//######################################################
+// ZQ:
+DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.
+
+// write leveling
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+
+//DQS gating, read delay, write delay calibration values based on calibration compare of 0x00ffff00:
+// It is highly recommended for the user to run calibration code on her/his specific board
+//and replace following delay values accordingly:
+
+
+
+//Read DQS Gating calibration
+DATA 4 0x021b083c 0x43480350
+DATA 4 0x021b0840 0x033C0340
+DATA 4 0x021b483c 0x43480350
+DATA 4 0x021b4840 0x03340314
+
+//Read calibration
+DATA 4 0x021b0848 0x382E2C32
+DATA 4 0x021b4848 0x38363044
+
+//Write calibration
+DATA 4 0x021b0850 0x3A38403A
+DATA 4 0x021b4850 0x4432483E
+
+
+
+//read data bit delay: (3 is the reccommended default value, although out of reset value is 0):
+DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3
+DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3
+DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3
+DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3
+DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3
+DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3
+DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3
+DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3
+
+
+//DATA 4 0x021b082c 0xf3333333 // wr bit delay, byte 0
+//DATA 4 0x021b0830 0xf3333333 // wr bit delay, byte 1
+//DATA 4 0x021b0834 0xf3333333 // wr bit delay, byte 2
+//DATA 4 0x021b0838 0xf3333333 // wr bit delay, byte 3
+//DATA 4 0x021b482c 0xf3333333 // wr bit delay, byte 4
+//DATA 4 0x021b4830 0xf3333333 // wr bit delay, byte 5
+//DATA 4 0x021b4834 0xf3333333 // wr bit delay, byte 6
+//DATA 4 0x021b4838 0xf3333333 // wr bit delay, byte 7
+
+
+//For i.mx6qd parts of versions A & B (v1.0, v1.1), uncomment the following lines. For version C (v1.2), keep commented
+//DATA 4 0x021b08c0 0x24911492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
+//DATA 4 0x021b48c0 0x24911492
+
+//######################################################
+// Complete calibration by forced measurment:
+//######################################################
+DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
+DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr
+
+//######################################################
+//MMDC init:
+
+
+//528MHz
+//in DDR3, 64-bit mode, only MMDC0 is initiated:
+DATA 4 0x021b0004 0x00020036 // MMDC0_MDPDC see spread sheet for timings
+DATA 4 0x021b0008 0x09444040 // MMDC0_MDOTC see spread sheet for timings
+DATA 4 0x021b000c 0x555A79A5 // MMDC0_MDCFG0 see spread sheet for timings. CL8
+DATA 4 0x021b0010 0xDB538E64 // MMDC0_MDCFG1 see spread sheet for timings
+DATA 4 0x021b0014 0x01ff00db // MMDC0_MDCFG2 - tRRD - 4ck; tWTR - 4ck; tRTP - 4ck; tDLLK - 512ck
+DATA 4 0x021b0018 0x00001740 // MMDC0_MDMISC, RALAT0x5
+//MDMISC: RALAT kept to the high level of 5.
+//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
+//a. better operation at low frequency
+//b. Small performence improvment
+
+DATA 4 0x021b001c 0x00008000 // MMDC0_MDSCR
+
+DATA 4 0x021b002c 0x000026d2 // MMDC0_MDRWD
+DATA 4 0x021b0030 0x005a1023 // MMDC0_MDOR - tXPR - 91ck; SDE_to_RST - 13ck; RST_to_CKE - 32ck //jimmy
+DATA 4 0x021b0040 0x00000027 // CS0_END - 0x4fffffff
+
+
+
+
+DATA 4 0x021b0000 0x831a0000 // MMDC0_MDCTL - row - 14bits; col 10bits; burst length 8; 64-bit data bus
+
+
+
+//######################################################
+// Initialize 2GB DDR3 - Micron MT41J128M , but fit wide range of other DDR3 devices
+//MR2:
+DATA 4 0x021b001c 0x04088032 // MMDC0_MDSCR
+DATA 4 0x021b001c 0x0408803a // MMDC0_MDSCR
+
+
+//MR3:
+DATA 4 0x021b001c 0x00008033 // MMDC0_MDSCR
+DATA 4 0x021b001c 0x0000803b // MMDC0_MDSCR
+//MR1:
+DATA 4 0x021b001c 0x00048031 // MMDC0_MDSCR
+DATA 4 0x021b001c 0x00048039 // MMDC0_MDSCR
+//MR0:
+
+DATA 4 0x021b001c 0x09408030 // MMDC0_MDSCR,
+DATA 4 0x021b001c 0x09408038 // MMDC0_MDSCR,
+
+//DDR device ZQ calibration:
+DATA 4 0x021b001c 0x04008040 // MMDC0_MDSCR,
+DATA 4 0x021b001c 0x04008048 // MMDC0_MDSCR
+//######################################################
+//final DDR setup, before operation start:
+
+DATA 4 0x021b0020 0x00005800 // MMDC0_MDREF, enable auto refresh, set refresh rate.
+
+//Following ODT setup (0x11117) represents(along with obove DDR device configs) : i.mx_ODTDDR_device_ODT120OHm.
+//User might to also interested in trying the value of 0x00000007,which represents: i.mx_ODT disabled, DDR_device_ODT120Ohm.
+//0x00000007 saves more power, and seen to run very well with Freescale RDKs. Still, running with no ODT has it's implications
+// of signal integrity and should be carefully simulated during board design.
+
+DATA 4 0x021b0818 0x00033337 // DDR_PHY_P0_MPODTCTRL, ODT enable
+DATA 4 0x021b4818 0x00033337 // DDR_PHY_P1_MPODTCTRL
+
+DATA 4 0x021b0004 0x00025576 // MMDC0_MDPDC see spread sheet for timings, SDCTL power down enabled
+
+DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled
+
+DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR
+
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en 1 --> CKO1 enabled
+ * cko1_div 111 --> divide by 8
+ * cko1_sel 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 132/8 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
diff --git a/configs/ge_elo_yocto_1g_defconfig b/configs/ge_elo_yocto_1g_defconfig
new file mode 100644
index 0000000..978b336
--- /dev/null
+++ b/configs/ge_elo_yocto_1g_defconfig
@@ -0,0 +1,10 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_GE_ELO=y
+CONFIG_SYS_DDR_1G=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_YOCTO_IMAGE=y
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 5219746..4aaccaa 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -52,7 +52,11 @@
#define CONFIG_RFSPART "1"
#endif
+#ifdef CONFIG_SYS_DDR_1G
+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+#else
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
+#endif
#define CONFIG_SUPPORT_EMMC_BOOT
--
2.5.0

59
recipes-bsp/u-boot/u-boot-ge-2015.10/0007-board-ge-bx50v3-Add-correct-SATA-settings.patch
View File

@ -1,59 +0,0 @@
From 660d9fe934bd3dcb0dde077d6f51adf8fc4fc779 Mon Sep 17 00:00:00 2001
From: Justin Waters <justin.waters@timesys.com>
Date: Tue, 19 Apr 2016 14:36:16 -0400
Subject: [PATCH 7/7] board: ge: bx50v3: Add correct SATA settings
Signed-off-by: Justin Waters <justin.waters@timesys.com>
---
board/ge/bx50v3/bx50v3.c | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 8d3e47a..18cac38 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -698,6 +698,30 @@ static iomux_v3_cfg_t const misc_pads[] = {
#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
#define WIFI_EN IMX_GPIO_NR(6, 14)
+int setup_ba16_sata(void)
+{
+ struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ int ret;
+
+ ret = enable_sata_clock();
+ if (ret)
+ return ret;
+
+ clrsetbits_le32(&iomuxc_regs->gpr[13],
+ IOMUXC_GPR13_SATA_MASK,
+ IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+ |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+ |IOMUXC_GPR13_SATA_SPEED_3G
+ |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+ |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+ |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
+ |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
+ |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
+ |IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+ return 0;
+}
+
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(misc_pads,
@@ -755,6 +779,10 @@ int board_late_init(void)
/* Backlight Power */
gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
+#ifdef CONFIG_CMD_SATA
+ setup_ba16_sata();
+#endif
+
return 0;
}
--
2.5.0

22
recipes-bsp/u-boot/u-boot-ge_2015.10.bb
View File

@ -1,22 +0,0 @@
require recipes-bsp/u-boot/u-boot.inc
DESCRIPTION = "U-Boot for GE i.MX6 BA16 based platforms"
LICENSE = "GPLv2+"
LIC_FILES_CHKSUM = "file://Licenses/README;md5=0507cd7da8e7ad6d6701926ec9b84c95"
DEPENDS = "u-boot-mkimage-native"
PROVIDES = "u-boot"
SRCREV = "1b6aee73e60023ae4ba16b11ce7bc23e0e8552f7"
SRC_URI = "git://github.com/Freescale/u-boot-fslc.git;branch=2015.10+fslc \
file://0001-arm-imx-Add-support-for-GE-Bx50v3-boards.patch \
file://0002-board-ge-bx50v3-Update-display-setup.patch \
file://0003-ge_bx50v3-Add-support-for-FSL-Community-Yocto-images.patch \
file://0004-board-ge-bx50v3-Add-support-for-ELO-board.patch \
file://0005-board-ge-bx50v3-Fix-bootargs-for-ELO-board.patch \
file://0006-mx6q_ba16-Add-1G-DDR-support.patch \
file://0007-board-ge-bx50v3-Add-correct-SATA-settings.patch \
"
PACKAGE_ARCH = "${MACHINE_ARCH}"
COMPATIBLE_MACHINE = "(imx6q-elo)"