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linux-fslc: ccimx6ul: Adapt to v4.20

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* Adapt patches to v4.20
* Remove patches that are already included in the v4.20 kernel

Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
This commit is contained in:
Alex Gonzalez 2019-02-26 10:29:15 +01:00 committed by Otavio Salvador
parent c4b5ac6b20
commit 545e8094a1
4 changed files with 18 additions and 171 deletions
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36
recipes-kernel/linux/linux-fslc/ccimx6ul/0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch
View File

@ -58,10 +58,10 @@ Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
3 files changed, 248 insertions(+), 49 deletions(-)
diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c
index 88ea2203e263..a4cd9523e220 100644
index a4768df5083f..72ace805f8c6 100644
--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c
+++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c
@@ -212,7 +212,8 @@ void gpmi_dump_info(struct gpmi_nand_data *this)
@@ -213,7 +213,8 @@ void gpmi_dump_info(struct gpmi_nand_data *this)
"ECC Strength : %u\n"
"Page Size in Bytes : %u\n"
"Metadata Size in Bytes : %u\n"
@ -71,7 +71,7 @@ index 88ea2203e263..a4cd9523e220 100644
"ECC Chunk Count : %u\n"
"Payload Size in Bytes : %u\n"
"Auxiliary Size in Bytes: %u\n"
@@ -223,7 +224,8 @@ void gpmi_dump_info(struct gpmi_nand_data *this)
@@ -224,7 +225,8 @@ void gpmi_dump_info(struct gpmi_nand_data *this)
geo->ecc_strength,
geo->page_size,
geo->metadata_size,
@ -81,7 +81,7 @@ index 88ea2203e263..a4cd9523e220 100644
geo->ecc_chunk_count,
geo->payload_size,
geo->auxiliary_size,
@@ -238,7 +240,8 @@ int bch_set_geometry(struct gpmi_nand_data *this)
@@ -239,7 +241,8 @@ int bch_set_geometry(struct gpmi_nand_data *this)
struct resources *r = &this->resources;
struct bch_geometry *bch_geo = &this->bch_geometry;
unsigned int block_count;
@ -91,7 +91,7 @@ index 88ea2203e263..a4cd9523e220 100644
unsigned int metadata_size;
unsigned int ecc_strength;
unsigned int page_size;
@@ -250,7 +253,8 @@ int bch_set_geometry(struct gpmi_nand_data *this)
@@ -251,7 +254,8 @@ int bch_set_geometry(struct gpmi_nand_data *this)
return ret;
block_count = bch_geo->ecc_chunk_count - 1;
@ -101,7 +101,7 @@ index 88ea2203e263..a4cd9523e220 100644
metadata_size = bch_geo->metadata_size;
ecc_strength = bch_geo->ecc_strength >> 1;
page_size = bch_geo->page_size;
@@ -277,13 +281,13 @@ int bch_set_geometry(struct gpmi_nand_data *this)
@@ -276,13 +280,13 @@ int bch_set_geometry(struct gpmi_nand_data *this)
| BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
| BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
| BF_BCH_FLASH0LAYOUT0_GF(gf_len, this)
@ -118,7 +118,7 @@ index 88ea2203e263..a4cd9523e220 100644
/* Set *all* chip selects to use layout 0. */
diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
index 1c1ebbc82824..bc4a364e5696 100644
index ed405c9434fe..0dd9d586a934 100644
--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
@@ -179,6 +179,36 @@ static inline bool gpmi_check_ecc(struct gpmi_nand_data *this)
@ -373,7 +373,7 @@ index 1c1ebbc82824..bc4a364e5696 100644
}
struct dma_chan *get_dma_chan(struct gpmi_nand_data *this)
@@ -997,7 +1156,8 @@ static int gpmi_ecc_read_page_data(struct nand_chip *chip,
@@ -991,7 +1150,8 @@ static int gpmi_ecc_read_page_data(struct nand_chip *chip,
/* Read ECC bytes into our internal raw_buffer */
offset = nfc_geo->metadata_size * 8;
@ -383,7 +383,7 @@ index 1c1ebbc82824..bc4a364e5696 100644
offset -= eccbits;
bitoffset = offset % 8;
eccbytes = DIV_ROUND_UP(offset + eccbits, 8);
@@ -1034,19 +1194,19 @@ static int gpmi_ecc_read_page_data(struct nand_chip *chip,
@@ -1028,19 +1188,19 @@ static int gpmi_ecc_read_page_data(struct nand_chip *chip,
if (i == 0) {
/* The first block includes metadata */
flips = nand_check_erased_ecc_chunk(
@ -414,7 +414,7 @@ index 1c1ebbc82824..bc4a364e5696 100644
}
if (flips > 0) {
@@ -1134,9 +1294,24 @@ static int gpmi_ecc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
@@ -1128,9 +1288,24 @@ static int gpmi_ecc_read_subpage(struct nand_chip *chip, uint32_t offs,
}
}
@ -436,11 +436,11 @@ index 1c1ebbc82824..bc4a364e5696 100644
+ else
+ col = meta + (size + ecc_parity_size) * first;
+
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, col, -1);
+ chip->legacy.cmdfunc(chip, NAND_CMD_RNDOUT, col, -1);
meta = 0;
buf = buf + first * size;
}
@@ -1149,21 +1324,37 @@ static int gpmi_ecc_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
@@ -1143,21 +1318,37 @@ static int gpmi_ecc_read_subpage(struct nand_chip *chip, uint32_t offs,
/* change the BCH registers and bch_geometry{} */
n = last - first + 1;
@ -481,8 +481,8 @@ index 1c1ebbc82824..bc4a364e5696 100644
geo->auxiliary_status_offset = ALIGN(meta, 4);
dev_dbg(this->dev, "page:%d(%d:%d)%d, chunk:(%d:%d), BCH PG size:%d\n",
@@ -1386,7 +1577,7 @@ static int gpmi_ecc_read_page_raw(struct mtd_info *mtd,
{
@@ -1381,7 +1572,7 @@ static int gpmi_ecc_read_page_raw(struct nand_chip *chip, uint8_t *buf,
struct mtd_info *mtd = nand_to_mtd(chip);
struct gpmi_nand_data *this = nand_get_controller_data(chip);
struct bch_geometry *nfc_geo = &this->bch_geometry;
- int eccsize = nfc_geo->ecc_chunk_size;
@ -490,8 +490,8 @@ index 1c1ebbc82824..bc4a364e5696 100644
int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len;
u8 *tmp_buf = this->raw_buffer;
size_t src_bit_off;
@@ -1471,7 +1662,7 @@ static int gpmi_ecc_write_page_raw(struct mtd_info *mtd,
{
@@ -1465,7 +1656,7 @@ static int gpmi_ecc_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
struct mtd_info *mtd = nand_to_mtd(chip);
struct gpmi_nand_data *this = nand_get_controller_data(chip);
struct bch_geometry *nfc_geo = &this->bch_geometry;
- int eccsize = nfc_geo->ecc_chunk_size;
@ -499,7 +499,7 @@ index 1c1ebbc82824..bc4a364e5696 100644
int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len;
u8 *tmp_buf = this->raw_buffer;
uint8_t *oob = chip->oob_poi;
@@ -1847,7 +2038,7 @@ static int gpmi_init_last(struct gpmi_nand_data *this)
@@ -1845,7 +2036,7 @@ static int gpmi_init_last(struct gpmi_nand_data *this)
ecc->read_oob_raw = gpmi_ecc_read_oob_raw;
ecc->write_oob_raw = gpmi_ecc_write_oob_raw;
ecc->mode = NAND_ECC_HW;
@ -509,7 +509,7 @@ index 1c1ebbc82824..bc4a364e5696 100644
mtd_set_ooblayout(mtd, &gpmi_ooblayout_ops);
diff --git a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
index 69cd0cbde4f2..ef4e57256d30 100644
index d0b79bac2728..4a9dab7c0859 100644
--- a/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
+++ b/drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.h
@@ -30,9 +30,9 @@ struct resources {

113
recipes-kernel/linux/linux-fslc/ccimx6ul/0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch
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@ -1,113 +0,0 @@
From: Anson Huang <Anson.Huang@nxp.com>
Date: Mon, 8 Oct 2018 14:07:34 +0800
Subject: [PATCH] cpufreq: imx6q: read OCOTP through nvmem for imx6ul/imx6ull
On i.MX6UL/i.MX6ULL, accessing OCOTP directly is wrong because
the ocotp clock needs to be enabled first. Add support for reading
OCOTP through the nvmem API, and keep the old method there to
support old dtb.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
(cherry picked from commit 2733fb0d0699246711cf622e0e2faf02a05b69dc)
---
drivers/cpufreq/imx6q-cpufreq.c | 52 +++++++++++++++++++++++++++--------------
1 file changed, 35 insertions(+), 17 deletions(-)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index b2ff423ad7f8..8cfee0ab804b 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -12,6 +12,7 @@
#include <linux/cpu_cooling.h>
#include <linux/err.h>
#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_opp.h>
@@ -290,20 +291,32 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
-static void imx6ul_opp_check_speed_grading(struct device *dev)
+static int imx6ul_opp_check_speed_grading(struct device *dev)
{
- struct device_node *np;
- void __iomem *base;
u32 val;
+ int ret = 0;
- np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
- if (!np)
- return;
+ if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
+ ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
+ if (ret)
+ return ret;
+ } else {
+ struct device_node *np;
+ void __iomem *base;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
+ if (!np)
+ return -ENOENT;
+
+ base = of_iomap(np, 0);
+ of_node_put(np);
+ if (!base) {
+ dev_err(dev, "failed to map ocotp\n");
+ return -EFAULT;
+ }
- base = of_iomap(np, 0);
- if (!base) {
- dev_err(dev, "failed to map ocotp\n");
- goto put_node;
+ val = readl_relaxed(base + OCOTP_CFG3);
+ iounmap(base);
}
/*
@@ -314,7 +327,6 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
* 2b'11: 900000000Hz on i.MX6ULL only;
* We need to set the max speed of ARM according to fuse map.
*/
- val = readl_relaxed(base + OCOTP_CFG3);
val >>= OCOTP_CFG3_SPEED_SHIFT;
val &= 0x3;
@@ -334,9 +346,7 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
dev_warn(dev, "failed to disable 900MHz OPP\n");
}
- iounmap(base);
-put_node:
- of_node_put(np);
+ return ret;
}
static int imx6q_cpufreq_probe(struct platform_device *pdev)
@@ -394,10 +404,18 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
}
if (of_machine_is_compatible("fsl,imx6ul") ||
- of_machine_is_compatible("fsl,imx6ull"))
- imx6ul_opp_check_speed_grading(cpu_dev);
- else
+ of_machine_is_compatible("fsl,imx6ull")) {
+ ret = imx6ul_opp_check_speed_grading(cpu_dev);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ if (ret) {
+ dev_err(cpu_dev, "failed to read ocotp: %d\n",
+ ret);
+ return ret;
+ }
+ } else {
imx6q_opp_check_speed_grading(cpu_dev);
+ }
/* Because we have added the OPPs here, we must free them */
free_opp = true;

38
recipes-kernel/linux/linux-fslc/ccimx6ul/0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch
View File

@ -1,38 +0,0 @@
From: Anson Huang <Anson.Huang@nxp.com>
Date: Fri, 14 Sep 2018 10:59:21 +0800
Subject: [PATCH] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first, so use the nvmem-cells binding instead.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
(cherry picked from commit 92f0eb08c66a73594cf200e65689e767f7f0da5e)
---
arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 6dc0b569acdf..c670d8e4e0a9 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -89,6 +89,8 @@
"pll1_sys";
arm-supply = <&reg_arm>;
soc-supply = <&reg_soc>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
};
@@ -932,6 +934,10 @@
tempmon_temp_grade: temp-grade@20 {
reg = <0x20 4>;
};
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
lcdif: lcdif@21c8000 {

2
recipes-kernel/linux/linux-fslc_%.bbappend
View File

@ -10,8 +10,6 @@ SRC_URI_append_imx6qdl-variscite-som_use-mainline-bsp = " \
SRC_URI_append_ccimx6ul = " \
file://0001-MLK-11719-4-mtd-gpmi-change-the-BCH-layout-setting-f.patch \
file://0002-cpufreq-imx6q-read-OCOTP-through-nvmem-for-imx6ul-im.patch \
file://0003-ARM-dts-imx6ul-use-nvmem-cells-for-cpu-speed-grading.patch \
"
do_configure_prepend_imx6qdl-variscite-som() {