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atf: introduce lx2160acex7 support

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Add support for platform build upon Solid-Run's new COM Express Type 7
for NXPs LX2160A (https://www.solid-run.com/nxp-lx2160a-family/cex7-lx2160/)
to ARM Trusted Firmware implementation.

Signed-off-by: Jens Rehsack <sno@netbsd.org>
This commit is contained in:
Jens Rehsack 2020-06-11 17:28:13 +02:00 committed by Otavio Salvador
parent 8ca8ce1ba0
commit c897e8a9ed
3 changed files with 570 additions and 0 deletions
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370
recipes-bsp/atf/atf-lx2160acex7/0001-plat-nxp-Add-lx2160acex7-module-support.patch Normal file
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@ -0,0 +1,370 @@
From 64bd53306e0301e707a52be9f4f7121c87cd6f7d Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 13:17:54 +0300
Subject: [PATCH] plat/nxp: Add lx2160acex7 module support
Adds SolidRun's LX2160A based SoC COM express type 7 module support.
The patch is based on LX2160ARDB board and modifies the support to two
SO-DIMMs DDR4 support on I2C address 0x50 and 0x52.
Upstream-Status: Inappropriate [Solid-Run BSP]
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
plat/nxp/soc-lx2160/lx2160acex7/ddr_init.c | 77 ++++++++
plat/nxp/soc-lx2160/lx2160acex7/platform.mk | 16 ++
.../nxp/soc-lx2160/lx2160acex7/platform_def.h | 187 ++++++++++++++++++
plat/nxp/soc-lx2160/lx2160acex7/policy.h | 40 ++++
4 files changed, 320 insertions(+)
create mode 100644 plat/nxp/soc-lx2160/lx2160acex7/ddr_init.c
create mode 100644 plat/nxp/soc-lx2160/lx2160acex7/platform.mk
create mode 100644 plat/nxp/soc-lx2160/lx2160acex7/platform_def.h
create mode 100644 plat/nxp/soc-lx2160/lx2160acex7/policy.h
diff --git a/plat/nxp/soc-lx2160/lx2160acex7/ddr_init.c b/plat/nxp/soc-lx2160/lx2160acex7/ddr_init.c
new file mode 100644
index 00000000..d0bcdf46
--- /dev/null
+++ b/plat/nxp/soc-lx2160/lx2160acex7/ddr_init.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2019 SolidRun ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Author Rabeeh Khoury <rabeeh@solid-run.com>
+ */
+
+#include <platform_def.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <debug.h>
+#include <errno.h>
+#include <utils.h>
+#include <string.h>
+#include <ddr.h>
+#include <i2c.h>
+
+int ddr_board_options(struct ddr_info *priv)
+{
+ struct memctl_opt *popts = &priv->opt;
+
+ popts->vref_dimm = 0x24; /* range 1, 83.4% */
+ popts->rtt_override = 0;
+ popts->rtt_park = 240;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ popts->trwt_override = 1;
+ popts->bstopre = 0; /* auto precharge */
+ popts->addr_hash = 1;
+ popts->trwt = 0x3;
+ popts->twrt = 0x3;
+ popts->trrt = 0x3;
+ popts->twwt = 0x3;
+ popts->vref_phy = 0x60; /* 75% */
+ popts->odt = 48;
+ popts->phy_tx_impedance = 48;
+
+ return 0;
+}
+
+long long _init_ddr(void)
+{
+ int spd_addr[] = { 0x51, 0x53 };
+ struct ddr_info info;
+ struct sysinfo sys;
+ long long dram_size;
+
+ zeromem(&sys, sizeof(sys));
+ get_clocks(&sys);
+ debug("platform clock %lu\n", sys.freq_platform);
+ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+ zeromem(&info, sizeof(info));
+
+ /* Set two DDRC. Unused DDRC will be removed automatically. */
+ info.num_ctlrs = 2;
+ info.spd_addr = spd_addr;
+ info.ddr[0] = (void *)NXP_DDR_ADDR;
+ info.ddr[1] = (void *)NXP_DDR2_ADDR;
+ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR;
+ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR;
+ info.clk = get_ddr_freq(&sys, 0);
+ if (!info.clk)
+ info.clk = get_ddr_freq(&sys, 1);
+ info.dimm_on_ctlr = 1;
+
+ dram_size = dram_init(&info);
+
+ if (dram_size < 0)
+ ERROR("DDR init failed.\n");
+
+ return dram_size;
+}
diff --git a/plat/nxp/soc-lx2160/lx2160acex7/platform.mk b/plat/nxp/soc-lx2160/lx2160acex7/platform.mk
new file mode 100644
index 00000000..490f82f8
--- /dev/null
+++ b/plat/nxp/soc-lx2160/lx2160acex7/platform.mk
@@ -0,0 +1,16 @@
+#
+# Copyright 2019 SolidRun ltd.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Author Rabeeh Khoury <rabeeh@solid-run.com>
+
+# board-specific build parameters
+BOOT_MODE := flexspi_nor
+BOARD := acex7
+
+ # get SoC common build parameters
+include plat/nxp/soc-lx2160/soc.mk
+
+BL2_SOURCES += ${BOARD_PATH}/ddr_init.c
+
diff --git a/plat/nxp/soc-lx2160/lx2160acex7/platform_def.h b/plat/nxp/soc-lx2160/lx2160acex7/platform_def.h
new file mode 100644
index 00000000..614f0342
--- /dev/null
+++ b/plat/nxp/soc-lx2160/lx2160acex7/platform_def.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2019 SolidRun ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Author: Rabeeh Khoury <rabeeh@solid-run.com>
+ */
+
+#ifndef __PLATFORM_DEF_H__
+#define __PLATFORM_DEF_H__
+
+#include <arch.h>
+/* Certain ARM files require defines from this file */
+#include <tbbr_img_def.h>
+/* From ARM :-> Has some common defines ARM requires */
+#include <common_def.h>
+/* Soc specific defines */
+#include <soc.h>
+/* include the platform-level security policy */
+#include <policy.h>
+
+#if defined(IMAGE_BL2)
+#define SEC_MEM_NON_COHERENT
+#endif
+/* Special value used to verify platform parameters from BL2 to BL31 */
+
+/* TBD -- Check and get back if this value is same for all platforms */
+#define LS_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
+
+/******************************************************************************
+ * Board specific defines
+ *****************************************************************************/
+
+#define NXP_SYSCLK_FREQ 100000000
+#define NXP_DDRCLK_FREQ 100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE 115200
+
+#define NXP_SPD_EEPROM0 0x51
+
+#define DDRC_NUM_DIMM 1
+#define CONFIG_DDR_ECC_EN
+#define CONFIG_DDR_ADDR_DEC /* enable address decoding feature */
+
+#define PLAT_DEF_DRAM0_SIZE 0x80000000 /* 2G */
+
+/* Board specific - size of QSPI Flash on board */
+#if FLEXSPI_NOR_BOOT
+#define NXP_FLEXSPI_FLASH_SIZE 0x10000000
+#endif
+/* TBD Put all memory specific defines here */
+
+/******************************************************************************
+ * Required platform porting definitions common to all ARM standard platforms
+ *****************************************************************************/
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE 0x2000
+#else
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+
+#define FIRMWARE_WELCOME_STR_LS_BL2 "Welcome to LX2160 BL2 Phase\n"
+#define FIRMWARE_WELCOME_STR_LS_BL31 "Welcome to LX2160 BL31 Phase\n"
+
+/* This is common for all platforms where
+ * 64K is reserved for Secure memory
+ */
+/* 64M Secure Memory */
+#define NXP_SECURE_DRAM_SIZE (64 * 1024 * 1024)
+
+/* 2M Secure EL1 Payload Shared Memory */
+#define NXP_SP_SHRD_DRAM_SIZE (2 * 1024 * 1024)
+
+/* Non secure memory */
+#define NXP_NS_DRAM_SIZE (NXP_DRAM0_SIZE - \
+ (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE))
+
+#define NXP_NS_DRAM_ADDR NXP_DRAM0_ADDR
+
+#ifdef TEST_BL31
+#define NXP_SECURE_DRAM_ADDR 0
+#else
+#define NXP_SECURE_DRAM_ADDR (NXP_NS_DRAM_ADDR + NXP_DRAM0_SIZE - \
+ (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE))
+#endif
+
+#define NXP_SP_SHRD_DRAM_ADDR (NXP_NS_DRAM_ADDR + NXP_DRAM0_SIZE \
+ - NXP_SP_SHRD_DRAM_SIZE)
+
+#define BL2_BASE (NXP_OCRAM_ADDR + NXP_ROM_RSVD + CSF_HDR_SZ)
+#ifdef SD_BOOT
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE - NXP_SD_BLOCK_BUF_SIZE)
+#else
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+#endif
+#define BL2_TEXT_LIMIT (BL2_LIMIT)
+
+/* 2 MB reserved in secure memory for DDR */
+#define BL31_BASE NXP_SECURE_DRAM_ADDR
+#define BL31_SIZE (0x200000)
+#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
+
+/* Put BL32 in secure memory */
+#define BL32_BASE (NXP_SECURE_DRAM_ADDR + BL31_SIZE)
+#define BL32_LIMIT (NXP_SECURE_DRAM_ADDR + \
+ NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)
+
+/* BL33 memory region */
+/* Hardcoded based on current address in u-boot */
+#define BL33_BASE 0x82000000
+#define BL33_LIMIT (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE)
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE (0xC000)
+#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE - NXP_SD_BLOCK_BUF_SIZE)
+
+#define PHY_GEN2_FW_IMAGE_BUFFER (ULL(0x18000000) + CSF_HDR_SZ)
+
+/* IO defines as needed by IO driver framework */
+/* TBD Add how to reach these numbers */
+#define MAX_IO_DEVICES 4
+#define MAX_IO_BLOCK_DEVICES 1
+#define MAX_IO_HANDLES 4
+
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES 3
+#define FUSE_BUF ULL(0x81000000)
+#define FUSE_SZ 0x80000
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES 2
+#endif
+
+#define PLAT_FIP_OFFSET 0x100000
+#define PLAT_FIP_MAX_SIZE 0x400000
+
+/* Check if this size can be determined from array size */
+#if defined(IMAGE_BL2)
+#define MAX_MMAP_REGIONS 8
+#define MAX_XLAT_TABLES 6
+#elif defined(IMAGE_BL31)
+#define MAX_MMAP_REGIONS 9
+#define MAX_XLAT_TABLES 9
+#elif defined(IMAGE_BL32)
+#define MAX_MMAP_REGIONS 8
+#define MAX_XLAT_TABLES 9
+#endif
+
+/******************************************************************************/
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER 29
+
+#define BL31_WDOG_SEC 89
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE)
+
+/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
+#define PLAT_LS_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+
+
+#endif
diff --git a/plat/nxp/soc-lx2160/lx2160acex7/policy.h b/plat/nxp/soc-lx2160/lx2160acex7/policy.h
new file mode 100644
index 00000000..deae979c
--- /dev/null
+++ b/plat/nxp/soc-lx2160/lx2160acex7/policy.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2019 SolidRun ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Author : Rabeeh Khoury <rabeeh@solid-run.com>
+ */
+
+/*---------------------------------------------------------------------------*/
+
+#ifndef _POLICY_H
+#define _POLICY_H
+
+ // the following defines affect the PLATFORM SECURITY POLICY
+
+ // set this to 0x0 if the platform is not using/responding to ECC errors
+ // set this to 0x1 if ECC is being used (we have to do some init)
+#define POLICY_USING_ECC 0x0
+
+ // Set this to 0x0 to leave the default SMMU page size in sACR
+ // Set this to 0x1 to change the SMMU page size to 64K
+#define POLICY_SMMU_PAGESZ_64K 0x1
+
+/*
+ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I
+ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7
+ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23
+ */
+#define POLICY_PERF_WRIOP 0
+
+ /*
+ * set this to '1' if the debug clocks need to remain enabled during
+ * system entry to low-power (LPM20) - this should only be necessary
+ * for testing and NEVER set for normal production
+ */
+#define POLICY_DEBUG_ENABLE 0
+
+//-----------------------------------------------------------------------------
+
+#endif // _POLICY_H
--
2.17.1

194
recipes-bsp/atf/atf-lx2160acex7/0002-plat-nxp-lx2160a-auto-boot.patch Normal file
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@ -0,0 +1,194 @@
From b5401a18ad8ade8f12a12171169f99214c7126e3 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Tue, 24 Mar 2020 02:48:34 +0200
Subject: [PATCH 2/2] plat/nxp: lx2160a auto boot
This patch adds support to patch RCW that already has SD/eMMC/SPI boot
support embedded with conditional load and jump.
The idea is to look for SD/eMMC/SPI boot, and modify src/dst/size
address with the correct values; rather than adding blockread at the end
of RCW code.
With this patch images are unified and can be used to boot from SD /
eMMC and SPI.
Upstream-Status: Inappropriate [Solid-Run BSP]
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
plat/nxp/common/common.mk | 5 +++
plat/nxp/tools/create_pbl.c | 79 ++++++++++++++++++++++++++++---------
2 files changed, 66 insertions(+), 18 deletions(-)
diff --git a/plat/nxp/common/common.mk b/plat/nxp/common/common.mk
index a80990740..e7e5f3879 100644
--- a/plat/nxp/common/common.mk
+++ b/plat/nxp/common/common.mk
@@ -148,6 +148,11 @@ BOOT_DEV_SOURCES = ${PLAT_DRIVERS_PATH}/sd/sd_mmc.c \
else ifeq (${BOOT_MODE}, flexspi_nor)
$(eval $(call add_define,FLEXSPI_NOR_BOOT))
BOOT_DEV_SOURCES = ${PLAT_DRIVERS_PATH}/flexspi/nor/flexspi_nor.c
+else ifeq (${BOOT_MODE}, auto)
+$(eval $(call add_define,FLEXSPI_NOR_BOOT))
+BOOT_DEV_SOURCES = ${PLAT_DRIVERS_PATH}/flexspi/nor/flexspi_nor.c \
+ ${PLAT_DRIVERS_PATH}/sd/sd_mmc.c \
+ drivers/io/io_block.c
endif
# DDR driver needs to be enabled by default
diff --git a/plat/nxp/tools/create_pbl.c b/plat/nxp/tools/create_pbl.c
index 5a08472be..7ee085757 100644
--- a/plat/nxp/tools/create_pbl.c
+++ b/plat/nxp/tools/create_pbl.c
@@ -67,6 +67,7 @@ typedef enum {
FLXSPI_NOR_BOOT,
FLXSPI_NAND_BOOT,
FLXSPI_NAND4K_BOOT,
+ AUTO_BOOT,
MAX_BOOT /* must be last item in list */
} boot_src_t;
@@ -194,7 +195,7 @@ struct pbl_image {
#define SOC_LS2088 2088
#define SOC_LX2160 2160
-static uint32_t pbl_size;
+static uint32_t pbl_size = 0;
bool sb_flag = false;
/***************************************************************************
@@ -503,7 +504,6 @@ int add_boot_ptr_cmd(FILE *fp_rcw_pbi_op)
goto bootptr_err;
}
}
-
printf("\nBoot Location Pointer= %x\n", BYTE_SWAP_32(pblimg.ep));
ret = SUCCESS;
@@ -697,6 +697,8 @@ int main(int argc, char **argv)
int ret = FAILURE;
bool bootptr_flag = false;
enum stop_command flag_stop_cmd = CRC_STOP_COMMAND;;
+ int skip = 0;
+ uint32_t saved_src;
/* Initializing the global structure to zero. */
memset(&pblimg, 0x0, sizeof(struct pbl_image));
@@ -797,6 +799,8 @@ int main(int argc, char **argv)
pblimg.boot_src = FLXSPI_NAND_BOOT;
else if (!strcmp(optarg, "flexspi_nand2k"))
pblimg.boot_src = FLXSPI_NAND4K_BOOT;
+ else if (!strcmp(optarg, "auto"))
+ pblimg.boot_src = AUTO_BOOT;
else {
printf("CMD Error: Invalid boot source.\n");
goto exit_main;
@@ -902,13 +906,14 @@ int main(int argc, char **argv)
printf("%s: Error reading PBI Cmd.\n", __func__);
goto exit_main;
}
- while (word != 0x808f0000 && word != 0x80ff0000) {
+ saved_src = pblimg.src_addr;
+ while (word != 0x808f0000 && word != 0x80ff0000) {
pbl_size++;
/* 11th words in RCW has PBL length. Update it
* with new length. 2 comamnds get added
* Block copy + CCSR Write/CSF header write
*/
- if (pbl_size == 11) {
+ if ((pbl_size == 11) && (pblimg.boot_src != AUTO_BOOT)) {
word_1 = (word & PBI_LEN_MASK)
+ (PBI_LEN_ADD << 20);
word = word & ~PBI_LEN_MASK;
@@ -923,8 +928,44 @@ int main(int argc, char **argv)
goto exit_main;
}
}
- if (fwrite(&word, sizeof(word), NUM_MEM_BLOCK,
- fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ if (pblimg.boot_src == AUTO_BOOT) {
+ if (word == 0x80000008) {
+ printf ("Found SD boot at %d\n",pbl_size);
+ pblimg.boot_src = SD_BOOT;
+ add_blk_cpy_cmd(fp_rcw_pbi_op, args);
+ pblimg.boot_src = AUTO_BOOT;
+ pblimg.src_addr = saved_src;
+ if (bootptr_flag == true) {
+ add_boot_ptr_cmd(fp_rcw_pbi_op);
+ skip = 6;
+ } else skip=4;
+ }
+ if (word == 0x80000009) {
+ printf ("Found eMMC boot at %d\n",pbl_size);
+ pblimg.boot_src = EMMC_BOOT;
+ add_blk_cpy_cmd(fp_rcw_pbi_op, args);
+ pblimg.boot_src = AUTO_BOOT;
+ pblimg.src_addr = saved_src;
+ if (bootptr_flag == true) {
+ add_boot_ptr_cmd(fp_rcw_pbi_op);
+ skip = 6;
+ } else skip=4;
+ }
+ if (word == 0x8000000f) {
+ printf ("Found SPI boot at %d\n",pbl_size);
+ pblimg.boot_src = FLXSPI_NOR_BOOT;
+ add_blk_cpy_cmd(fp_rcw_pbi_op, args);
+ pblimg.boot_src = AUTO_BOOT;
+ pblimg.src_addr = saved_src;
+ if (bootptr_flag == true) {
+ add_boot_ptr_cmd(fp_rcw_pbi_op);
+ skip = 6;
+ } else skip=4;
+ }
+ }
+ if (!skip &&
+ (fwrite(&word, sizeof(word), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK)) {
printf("%s: [CH3] Error in Writing PBI Words\n",
__func__);
goto exit_main;
@@ -941,8 +982,9 @@ int main(int argc, char **argv)
} else if (word == STOP_CMD_ARM_CH3){
flag_stop_cmd = STOP_COMMAND;
}
+ if (skip) skip--;
}
- if (bootptr_flag == true) {
+ if ((pblimg.boot_src != AUTO_BOOT) && (bootptr_flag == true)) {
/* Add command to set boot_loc ptr */
ret = add_boot_ptr_cmd(fp_rcw_pbi_op);
if (ret != SUCCESS) {
@@ -953,18 +995,19 @@ int main(int argc, char **argv)
}
/* Write acs write commands to output file */
- ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args);
- if (ret != SUCCESS) {
- printf("%s: Function add_blk_cpy_cmd return failure.\n",
- __func__);
- goto exit_main;
- }
-
+ if (pblimg.boot_src != AUTO_BOOT) {
+ ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args);
+ if (ret != SUCCESS) {
+ printf("%s: Function add_blk_cpy_cmd return failure.\n",
+ __func__);
+ goto exit_main;
+ }
+ }
/* Add stop command after adding pbi commands */
- ret = add_pbi_stop_cmd(fp_rcw_pbi_op, flag_stop_cmd);
- if (ret != SUCCESS) {
- goto exit_main;
- }
+ ret = add_pbi_stop_cmd(fp_rcw_pbi_op, flag_stop_cmd);
+ if (ret != SUCCESS) {
+ goto exit_main;
+ }
break;
--
2.17.1

6
recipes-bsp/atf/atf_git.bbappend Normal file
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@ -0,0 +1,6 @@
FILESEXTRAPATHS_append_lx2160acex7 := "${THISDIR}/${PN}-lx2160acex7:"
SRC_URI_append_lx2160acex7 = "\
file://0001-plat-nxp-Add-lx2160acex7-module-support.patch \
file://0002-plat-nxp-lx2160a-auto-boot.patch \
"