diff --git a/recipes-kernel/linux/linux-ge-3.14/0001-rtc-rx8010-Add-driver-to-kernel.patch b/recipes-kernel/linux/linux-ge-3.14/0001-rtc-rx8010-Add-driver-to-kernel.patch new file mode 100644 index 0000000..e88b71b --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/0001-rtc-rx8010-Add-driver-to-kernel.patch @@ -0,0 +1,1020 @@ +From fc70b949055cfcf19914e9ab1a6ab21d9e7e9634 Mon Sep 17 00:00:00 2001 +From: Justin Waters +Date: Mon, 22 Dec 2014 11:35:24 -0500 +Subject: [PATCH 01/10] rtc-rx8010: Add driver to kernel + +This is the rx810_k3.8-v1.3 version from the Epson support site: + +http://www5.epsondevice.com/en/quartz/tech/linux_for_rtc/software/rx8010_k3.8-v1.3.zip +--- + drivers/rtc/Kconfig | 8 + + drivers/rtc/Makefile | 1 + + drivers/rtc/rtc-rx8010.c | 965 +++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 974 insertions(+) + create mode 100644 drivers/rtc/rtc-rx8010.c + +diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig +index db933de..87ed3a3 100644 +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -494,6 +494,14 @@ config RTC_DRV_FM3130 + This driver can also be built as a module. If so the module + will be called rtc-fm3130. + ++config RTC_DRV_RX8010 ++ tristate "Epson RX-8010SJ" ++ help ++ If you say yes here you will get support for the Epson RX-8010SJ. ++ ++ This driver can also be built as a module. If so the module ++ will be called rtc-rx8010. ++ + config RTC_DRV_RX8581 + tristate "Epson RX-8581" + help +diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile +index b427bf7..1512f48 100644 +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -106,6 +106,7 @@ obj-$(CONFIG_RTC_DRV_RS5C348) += rtc-rs5c348.o + obj-$(CONFIG_RTC_DRV_RS5C372) += rtc-rs5c372.o + obj-$(CONFIG_RTC_DRV_RV3029C2) += rtc-rv3029c2.o + obj-$(CONFIG_RTC_DRV_RX4581) += rtc-rx4581.o ++obj-$(CONFIG_RTC_DRV_RX8010) += rtc-rx8010.o + obj-$(CONFIG_RTC_DRV_RX8025) += rtc-rx8025.o + obj-$(CONFIG_RTC_DRV_RX8581) += rtc-rx8581.o + obj-$(CONFIG_RTC_DRV_S35390A) += rtc-s35390a.o +diff --git a/drivers/rtc/rtc-rx8010.c b/drivers/rtc/rtc-rx8010.c +new file mode 100644 +index 0000000..80f7506 +--- /dev/null ++++ b/drivers/rtc/rtc-rx8010.c +@@ -0,0 +1,965 @@ ++//====================================================================== ++// Driver for the Epson RTC module RX-8010 SJ ++// ++// Copyright(C) SEIKO EPSON CORPORATION 2013. All rights reserved. ++// ++// Derived from RX-8025 driver: ++// Copyright (C) 2009 Wolfgang Grandegger ++// ++// Copyright (C) 2005 by Digi International Inc. ++// All rights reserved. ++// ++// Modified by fengjh at rising.com.cn ++// ++// 2006.11 ++// ++// Code cleanup by Sergei Poselenov, ++// Converted to new style by Wolfgang Grandegger ++// Alarm and periodic interrupt added by Dmitry Rakhchev ++// ++// ++// This driver software is distributed as is, without any warranty of any kind, ++// either express or implied as further specified in the GNU Public License. This ++// software may be used and distributed according to the terms of the GNU Public ++// License, version 2 as published by the Free Software Foundation. ++// See the file COPYING in the main directory of this archive for more details. ++// ++// You should have received a copy of the GNU General Public License along with ++// this program. If not, see . ++//====================================================================== ++ ++#if 0 ++#define DEBUG ++#include ++#undef DEBUG ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++// RX-8010 Register definitions ++#define RX8010_REG_SEC 0x10 ++#define RX8010_REG_MIN 0x11 ++#define RX8010_REG_HOUR 0x12 ++#define RX8010_REG_WDAY 0x13 ++#define RX8010_REG_MDAY 0x14 ++#define RX8010_REG_MONTH 0x15 ++#define RX8010_REG_YEAR 0x16 ++// 0x17 is reserved ++#define RX8010_REG_ALMIN 0x18 ++#define RX8010_REG_ALHOUR 0x19 ++#define RX8010_REG_ALWDAY 0x1A ++#define RX8010_REG_TCOUNT0 0x1B ++#define RX8010_REG_TCOUNT1 0x1C ++#define RX8010_REG_EXT 0x1D ++#define RX8010_REG_FLAG 0x1E ++#define RX8010_REG_CTRL 0x1F ++#define RX8010_REG_USER0 0x20 ++#define RX8010_REG_USER1 0x21 ++#define RX8010_REG_USER2 0x22 ++#define RX8010_REG_USER3 0x23 ++#define RX8010_REG_USER4 0x24 ++#define RX8010_REG_USER5 0x25 ++#define RX8010_REG_USER6 0x26 ++#define RX8010_REG_USER7 0x27 ++#define RX8010_REG_USER8 0x28 ++#define RX8010_REG_USER9 0x29 ++#define RX8010_REG_USERA 0x2A ++#define RX8010_REG_USERB 0x2B ++#define RX8010_REG_USERC 0x2C ++#define RX8010_REG_USERD 0x2D ++#define RX8010_REG_USERE 0x2E ++#define RX8010_REG_USERF 0x2F ++// 0x30 is reserved ++// 0x31 is reserved ++#define RX8010_REG_IRQ 0x32 ++ ++// Extension Register (1Dh) bit positions ++#define RX8010_BIT_EXT_TSEL (7 << 0) ++#define RX8010_BIT_EXT_WADA (1 << 3) ++#define RX8010_BIT_EXT_TE (1 << 4) ++#define RX8010_BIT_EXT_USEL (1 << 5) ++#define RX8010_BIT_EXT_FSEL (3 << 6) ++ ++// Flag Register (1Eh) bit positions ++#define RX8010_BIT_FLAG_VLF (1 << 1) ++#define RX8010_BIT_FLAG_AF (1 << 3) ++#define RX8010_BIT_FLAG_TF (1 << 4) ++#define RX8010_BIT_FLAG_UF (1 << 5) ++ ++// Control Register (1Fh) bit positions ++#define RX8010_BIT_CTRL_TSTP (1 << 2) ++#define RX8010_BIT_CTRL_AIE (1 << 3) ++#define RX8010_BIT_CTRL_TIE (1 << 4) ++#define RX8010_BIT_CTRL_UIE (1 << 5) ++#define RX8010_BIT_CTRL_STOP (1 << 6) ++#define RX8010_BIT_CTRL_TEST (1 << 7) ++ ++ ++static const struct i2c_device_id rx8010_id[] = { ++ { "rx8010", 0 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(i2c, rx8010_id); ++ ++struct rx8010_data { ++ struct i2c_client *client; ++ struct rtc_device *rtc; ++ struct work_struct work_1; ++ struct work_struct work_2; ++ u8 ctrlreg; ++ int irq_1; ++ int irq_2; ++ unsigned exiting:1; ++}; ++ ++typedef struct { ++ u8 number; ++ u8 value; ++}reg_data; ++ ++#define SE_RTC_REG_READ _IOWR('p', 0x20, reg_data) ++#define SE_RTC_REG_WRITE _IOW('p', 0x21, reg_data) ++ ++//---------------------------------------------------------------------- ++// rx8010_read_reg() ++// reads a rx8010 register (see Register defines) ++// See also rx8010_read_regs() to read multiple registers. ++// ++//---------------------------------------------------------------------- ++static int rx8010_read_reg(struct i2c_client *client, int number, u8 *value) ++{ ++ int ret = i2c_smbus_read_byte_data(client, number) ; ++ ++ //check for error ++ if (ret < 0) { ++ dev_err(&client->dev, "Unable to read register #%d\n", number); ++ return ret; ++ } ++ ++ *value = ret; ++ return 0; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_read_regs() ++// reads a specified number of rx8010 registers (see Register defines) ++// See also rx8010_read_reg() to read single register. ++// ++//---------------------------------------------------------------------- ++static int rx8010_read_regs(struct i2c_client *client, int number, u8 length, u8 *values) ++{ ++ int ret = i2c_smbus_read_i2c_block_data(client, number, length, values); ++ ++ //check for length error ++ if (ret != length) { ++ dev_err(&client->dev, "Unable to read registers #%d..#%d\n", number, number + length - 1); ++ return ret < 0 ? ret : -EIO; ++ } ++ ++ return 0; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_write_reg() ++// writes a rx8010 register (see Register defines) ++// See also rx8010_write_regs() to write multiple registers. ++// ++//---------------------------------------------------------------------- ++static int rx8010_write_reg(struct i2c_client *client, int number, u8 value) ++{ ++ int ret = i2c_smbus_write_byte_data(client, number, value); ++ ++ //check for error ++ if (ret) ++ dev_err(&client->dev, "Unable to write register #%d\n", number); ++ ++ return ret; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_write_regs() ++// writes a specified number of rx8010 registers (see Register defines) ++// See also rx8010_write_reg() to write a single register. ++// ++//---------------------------------------------------------------------- ++static int rx8010_write_regs(struct i2c_client *client, int number, u8 length, u8 *values) ++{ ++ int ret = i2c_smbus_write_i2c_block_data(client, number, length, values); ++ ++ //check for error ++ if (ret) ++ dev_err(&client->dev, "Unable to write registers #%d..#%d\n", number, number + length - 1); ++ ++ return ret; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_irq_1() ++// irq handler ++// ++//---------------------------------------------------------------------- ++static irqreturn_t rx8010_irq_1(int irq, void *dev_id) ++{ ++ struct i2c_client *client = dev_id; ++ struct rx8010_data *rx8010 = i2c_get_clientdata(client); ++ ++ disable_irq_nosync(irq); ++ schedule_work(&rx8010->work_1); ++ ++ ++ return IRQ_HANDLED; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_work_1() ++// ++//---------------------------------------------------------------------- ++static void rx8010_work_1(struct work_struct *work) ++{ ++ struct rx8010_data *rx8010 = container_of(work, struct rx8010_data, work_1); ++ struct i2c_client *client = rx8010->client; ++ struct mutex *lock = &rx8010->rtc->ops_lock; ++ u8 status; ++ ++ mutex_lock(lock); ++ ++ if (rx8010_read_reg(client, RX8010_REG_FLAG, &status)) ++ goto out; ++ ++ // check VLF ++ if ((status & RX8010_BIT_FLAG_VLF)) ++ dev_warn(&client->dev, "Frequency stop was detected, probably due to a supply voltage drop\n"); ++ ++ dev_dbg(&client->dev, "%s: RX8010_REG_FLAG: %xh\n", __func__, status); ++ ++ // periodic "fixed-cycle" timer ++ if (status & RX8010_BIT_FLAG_TF) { ++ status &= ~RX8010_BIT_FLAG_TF; ++ local_irq_disable(); ++ rtc_update_irq(rx8010->rtc, 1, RTC_PF | RTC_IRQF); ++ local_irq_enable(); ++ } ++ ++ // alarm function ++ if (status & RX8010_BIT_FLAG_AF) { ++ status &= ~RX8010_BIT_FLAG_AF; ++ local_irq_disable(); ++ rtc_update_irq(rx8010->rtc, 1, RTC_AF | RTC_IRQF); ++ local_irq_enable(); ++ } ++ ++ // time update function ++ if (status & RX8010_BIT_FLAG_UF) { ++ status &= ~RX8010_BIT_FLAG_UF; ++ local_irq_disable(); ++ rtc_update_irq(rx8010->rtc, 1, RTC_UF | RTC_IRQF); ++ local_irq_enable(); ++ } ++ ++ // acknowledge IRQ (clear flags) ++ rx8010_write_reg(client, RX8010_REG_FLAG, status); ++ ++out: ++ if (!rx8010->exiting) ++ { ++ if (rx8010->irq_1 > 0) ++ enable_irq(rx8010->irq_1); ++ else ++ enable_irq(client->irq); ++ } ++ ++ mutex_unlock(lock); ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_irq_2() ++// irq handler ++// ++//---------------------------------------------------------------------- ++static irqreturn_t rx8010_irq_2(int irq, void *dev_id) ++{ ++ struct i2c_client *client = dev_id; ++ struct rx8010_data *rx8010 = i2c_get_clientdata(client); ++ ++ disable_irq_nosync(irq); ++ schedule_work(&rx8010->work_2); ++ ++ ++ return IRQ_HANDLED; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_work_2() ++// ++//---------------------------------------------------------------------- ++static void rx8010_work_2(struct work_struct *work) ++{ ++ struct rx8010_data *rx8010 = container_of(work, struct rx8010_data, work_2); ++ struct i2c_client *client = rx8010->client; ++ struct mutex *lock = &rx8010->rtc->ops_lock; ++ u8 status; ++ ++ mutex_lock(lock); ++ ++ if (rx8010_read_reg(client, RX8010_REG_FLAG, &status)) ++ goto out; ++ ++ // check VLF ++ if ((status & RX8010_BIT_FLAG_VLF)) ++ dev_warn(&client->dev, "Frequency stop was detected, \ ++ probably due to a supply voltage drop\n"); ++ ++ dev_dbg(&client->dev, "%s: RX8010_REG_FLAG: %xh\n", __func__, status); ++ ++ // periodic "fixed-cycle" timer ++ if (status & RX8010_BIT_FLAG_TF) { ++ status &= ~RX8010_BIT_FLAG_TF; ++ local_irq_disable(); ++ rtc_update_irq(rx8010->rtc, 1, RTC_PF | RTC_IRQF); ++ local_irq_enable(); ++ } ++ ++ // acknowledge IRQ (clear flags) ++ rx8010_write_reg(client, RX8010_REG_FLAG, status); ++ ++out: ++ if (!rx8010->exiting) ++ { ++ if (rx8010->irq_2 > 0) ++ enable_irq(rx8010->irq_2); ++ else ++ enable_irq(client->irq); ++ } ++ ++ mutex_unlock(lock); ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_get_time() ++// gets the current time from the rx8010 registers ++// ++//---------------------------------------------------------------------- ++static int rx8010_get_time(struct device *dev, struct rtc_time *dt) ++{ ++ struct rx8010_data *rx8010 = dev_get_drvdata(dev); ++ u8 date[7]; ++ int err; ++ ++ err = rx8010_read_regs(rx8010->client, RX8010_REG_SEC, 7, date); ++ if (err) ++ return err; ++ ++ dev_dbg(dev, "%s: read 0x%02x 0x%02x " ++ "0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", __func__, ++ date[0], date[1], date[2], date[3], date[4], date[5], date[6]); ++ ++ //Note: need to subtract 0x10 for index as register offset starts at 0x10 ++ dt->tm_sec = bcd2bin(date[RX8010_REG_SEC-0x10] & 0x7f); ++ dt->tm_min = bcd2bin(date[RX8010_REG_MIN-0x10] & 0x7f); ++ dt->tm_hour = bcd2bin(date[RX8010_REG_HOUR-0x10] & 0x3f); //only 24-hour clock ++ dt->tm_mday = bcd2bin(date[RX8010_REG_MDAY-0x10] & 0x3f); ++ dt->tm_mon = bcd2bin(date[RX8010_REG_MONTH-0x10] & 0x1f) - 1; ++ dt->tm_year = bcd2bin(date[RX8010_REG_YEAR-0x10]); ++ dt->tm_wday = bcd2bin(date[RX8010_REG_WDAY-0x10] & 0x7f); ++ ++ if (dt->tm_year < 70) ++ dt->tm_year += 100; ++ ++ dev_dbg(dev, "%s: date %ds %dm %dh %dmd %dm %dy\n", __func__, ++ dt->tm_sec, dt->tm_min, dt->tm_hour, ++ dt->tm_mday, dt->tm_mon, dt->tm_year); ++ ++ return rtc_valid_tm(dt); ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_set_time() ++// Sets the current time in the rx8010 registers ++// ++// BUG: The HW assumes every year that is a multiple of 4 to be a leap ++// year. Next time this is wrong is 2100, which will not be a leap year ++// ++// Note: If STOP is not set/cleared, the clock will start when the seconds ++// register is written ++// ++//---------------------------------------------------------------------- ++static int rx8010_set_time(struct device *dev, struct rtc_time *dt) ++{ ++ struct rx8010_data *rx8010 = dev_get_drvdata(dev); ++ u8 date[7]; ++ u8 ctrl; ++ int ret; ++ ++ //set STOP bit before changing clock/calendar ++ rx8010_read_reg(rx8010->client, RX8010_REG_CTRL, &ctrl); ++ rx8010->ctrlreg = ctrl | RX8010_BIT_CTRL_STOP; ++ rx8010_write_reg(rx8010->client, RX8010_REG_CTRL, rx8010->ctrlreg); ++ ++ //Note: need to subtract 0x10 for index as register offset starts at 0x10 ++ date[RX8010_REG_SEC-0x10] = bin2bcd(dt->tm_sec); ++ date[RX8010_REG_MIN-0x10] = bin2bcd(dt->tm_min); ++ date[RX8010_REG_HOUR-0x10] = bin2bcd(dt->tm_hour); //only 24hr time ++ ++ date[RX8010_REG_MDAY-0x10] = bin2bcd(dt->tm_mday); ++ date[RX8010_REG_MONTH-0x10] = bin2bcd(dt->tm_mon + 1); ++ date[RX8010_REG_YEAR-0x10] = bin2bcd(dt->tm_year % 100); ++ date[RX8010_REG_WDAY-0x10] = bin2bcd(dt->tm_wday); ++ ++ dev_dbg(dev, "%s: write 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", ++ __func__, date[0], date[1], date[2], date[3], date[4], date[5], date[6]); ++ ++ ret = rx8010_write_regs(rx8010->client, RX8010_REG_SEC, 7, date); ++ ++ //clear STOP bit after changing clock/calendar ++ rx8010_read_reg(rx8010->client, RX8010_REG_CTRL, &ctrl); ++ rx8010->ctrlreg = ctrl & ~RX8010_BIT_CTRL_STOP; ++ rx8010_write_reg(rx8010->client, RX8010_REG_CTRL, rx8010->ctrlreg); ++ ++ return ret; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_init_client() ++// initializes the rx8010 ++// ++//---------------------------------------------------------------------- ++static int rx8010_init_client(struct i2c_client *client, int *need_reset) ++{ ++ struct rx8010_data *rx8010 = i2c_get_clientdata(client); ++ u8 ctrl[3]; ++ int need_clear = 0; ++ int err; ++ ++ //set reserved register 0x17 with specified value of 0xD8 ++ err = rx8010_write_reg(client, 0x17, 0xD8); ++ if (err) ++ goto out; ++ ++ //set reserved register 0x30 with specified value of 0x00 ++ err = rx8010_write_reg(client, 0x30, 0x00); ++ if (err) ++ goto out; ++ ++ //set reserved register 0x31 with specified value of 0x08 ++ err = rx8010_write_reg(client, 0x31, 0x08); ++ if (err) ++ goto out; ++ ++ //set reserved register 0x32 with default value ++ err = rx8010_write_reg(client, RX8010_REG_IRQ, 0x00); ++ if (err) ++ goto out; ++ ++ ++ //get current extension, flag, control register values ++ err = rx8010_read_regs(rx8010->client, RX8010_REG_EXT, 3, ctrl); ++ if (err) ++ goto out; ++ ++ //check for VLF Flag (set at power-on) ++ if ((ctrl[1] & RX8010_BIT_FLAG_VLF)) { ++ dev_warn(&client->dev, "Frequency stop was detected, probably due to a supply voltage drop\n"); ++ *need_reset = 1; ++ } ++ ++ //check for Alarm Flag ++ if (ctrl[1] & RX8010_BIT_FLAG_AF) { ++ dev_warn(&client->dev, "Alarm was detected\n"); ++ need_clear = 1; ++ } ++ ++ //check for Periodic Timer Flag ++ if (ctrl[1] & RX8010_BIT_FLAG_TF) { ++ dev_warn(&client->dev, "Periodic timer was detected\n"); ++ need_clear = 1; ++ } ++ ++ //check for Update Timer Flag ++ if (ctrl[1] & RX8010_BIT_FLAG_UF) { ++ dev_warn(&client->dev, "Update timer was detected\n"); ++ need_clear = 1; ++ } ++ ++ //reset or clear needed? ++ if (*need_reset) { ++ //clear 1d, 1e, 1f registers ++ ctrl[0] = ctrl[1] = ctrl[2] = 0; ++ err = rx8010_write_regs(client, RX8010_REG_EXT, 3, ctrl); ++ if (err) ++ goto out; ++ } ++ else if(need_clear){ ++ //clear flag register ++ err = rx8010_write_reg(client, RX8010_REG_FLAG, 0x00); ++ if (err) ++ goto out; ++ } ++ ++ //set "test bit" and reserved bits of control register zero ++ rx8010->ctrlreg = (ctrl[2] & ~RX8010_BIT_CTRL_TEST); ++out: ++ return err; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_read_alarm() ++// reads current Alarm ++// ++// Notes: - currently filters the AE bits (bit 7) ++// - assumes WADA setting is week (week/day) ++//---------------------------------------------------------------------- ++static int rx8010_read_alarm(struct device *dev, struct rtc_wkalrm *t) ++{ ++ struct rx8010_data *rx8010 = dev_get_drvdata(dev); ++ struct i2c_client *client = rx8010->client; ++ u8 alarmvals[3]; //minute, hour, week/day values ++ u8 ctrl[3]; //extension, flag, control values ++ int err; ++ ++ if (client->irq <= 0) ++ return -EINVAL; ++ ++ //get current minute, hour, week/day alarm values ++ err = rx8010_read_regs(client, RX8010_REG_ALMIN, 3, alarmvals); ++ if (err) ++ return err; ++ dev_dbg(dev, "%s: minutes:0x%02x hours:0x%02x week/day:0x%02x\n", ++ __func__, alarmvals[0], alarmvals[1], alarmvals[2]); ++ ++ ++ //get current extension, flag, control register values ++ err = rx8010_read_regs(client, RX8010_REG_EXT, 3, ctrl); ++ if (err) ++ return err; ++ dev_dbg(dev, "%s: extension:0x%02x flag:0x%02x control:0x%02x \n", ++ __func__, ctrl[0], ctrl[1], ctrl[2]); ++ ++ // Hardware alarm precision is 1 minute ++ t->time.tm_sec = 0; ++ t->time.tm_min = bcd2bin(alarmvals[0] & 0x7f); //0x7f filters AE bit currently ++ t->time.tm_hour = bcd2bin(alarmvals[1] & 0x3f); //0x3f filters AE bit currently, also 24hr only ++ ++ t->time.tm_wday = -1; ++ t->time.tm_mday = -1; ++ t->time.tm_mon = -1; ++ t->time.tm_year = -1; ++ ++ dev_dbg(dev, "%s: date: %ds %dm %dh %dmd %dm %dy\n", ++ __func__, ++ t->time.tm_sec, t->time.tm_min, t->time.tm_hour, ++ t->time.tm_mday, t->time.tm_mon, t->time.tm_year); ++ ++ t->enabled = !!(rx8010->ctrlreg & RX8010_BIT_CTRL_AIE); //check if interrupt is enabled ++ t->pending = (ctrl[1] & RX8010_BIT_FLAG_AF) && t->enabled; //check if flag is triggered ++ ++ return err; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_set_alarm() ++// sets Alarm ++// ++// Notes: - currently filters the AE bits (bit 7) ++// - assumes WADA setting is week (week/day) ++//---------------------------------------------------------------------- ++static int rx8010_set_alarm(struct device *dev, struct rtc_wkalrm *t) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ struct rx8010_data *rx8010 = dev_get_drvdata(dev); ++ u8 alarmvals[3]; //minute, hour, day ++ u8 extreg; //extension register ++ u8 flagreg; //flag register ++ int err; ++ ++ if (client->irq <= 0) ++ return -EINVAL; ++ ++ //get current extension register ++ err = rx8010_read_reg(client, RX8010_REG_EXT, &extreg); ++ if (err <0) ++ return err; ++ ++ //get current flag register ++ err = rx8010_read_reg(client, RX8010_REG_FLAG, &flagreg); ++ if (err <0) ++ return err; ++ ++ // Hardware alarm precision is 1 minute ++ alarmvals[0] = bin2bcd(t->time.tm_min); ++ alarmvals[1] = bin2bcd(t->time.tm_hour); ++ alarmvals[2] = bin2bcd(t->time.tm_mday); ++ dev_dbg(dev, "%s: write 0x%02x 0x%02x 0x%02x\n", __func__, alarmvals[0], alarmvals[1], alarmvals[2]); ++ ++ //check interrupt enable and disable ++ if (rx8010->ctrlreg & RX8010_BIT_CTRL_AIE) { ++ rx8010->ctrlreg &= ~RX8010_BIT_CTRL_AIE; ++ err = rx8010_write_reg(rx8010->client, RX8010_REG_CTRL, rx8010->ctrlreg); ++ if (err) ++ return err; ++ } ++ ++ //write the new minute and hour values ++ //Note:assume minute and hour values will be enabled. Bit 7 of each of the ++ // minute, hour, week/day register can be set which will "disable" the ++ // register from triggering an alarm. See the RX8010 spec for more information ++ err = rx8010_write_regs(rx8010->client, RX8010_REG_ALMIN, 2, alarmvals); ++ if (err) ++ return err; ++ ++ //set Week/Day bit ++ // Week setting is typically not used, so we will assume "day" setting ++ extreg |= RX8010_BIT_EXT_WADA; //set to "day of month" ++ err = rx8010_write_reg(rx8010->client, RX8010_REG_EXT, extreg); ++ if (err) ++ return err; ++ ++ //set Day of Month register ++ if (alarmvals[2] == 0) { ++ alarmvals[2] |= 0x80; //turn on AE bit to ignore day of month (no zero day) ++ err = rx8010_write_reg(rx8010->client, RX8010_REG_ALWDAY, alarmvals[2]); ++ } ++ else { ++ err = rx8010_write_reg(rx8010->client, RX8010_REG_ALWDAY, alarmvals[2]); ++ } ++ if (err) ++ return err; ++ ++ //clear Alarm Flag ++ flagreg &= ~RX8010_BIT_FLAG_AF; ++ err = rx8010_write_reg(rx8010->client, RX8010_REG_FLAG, flagreg); ++ if (err) ++ return err; ++ ++ //re-enable interrupt if required ++ if (t->enabled) { ++ ++ if ( rx8010->rtc->uie_rtctimer.enabled ) ++ rx8010->ctrlreg |= RX8010_BIT_CTRL_UIE; //set update interrupt enable ++ if ( rx8010->rtc->aie_timer.enabled ) ++ rx8010->ctrlreg |= (RX8010_BIT_CTRL_AIE | RX8010_BIT_CTRL_UIE); //set alarm interrupt enable ++ ++ err = rx8010_write_reg(rx8010->client, RX8010_REG_CTRL, rx8010->ctrlreg); ++ if (err) ++ return err; ++ } ++ ++ return 0; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_alarm_irq_enable() ++// sets enables Alarm IRQ ++// ++// Todo: - ++// ++//---------------------------------------------------------------------- ++static int rx8010_alarm_irq_enable(struct device *dev, unsigned int enabled) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ struct rx8010_data *rx8010 = dev_get_drvdata(dev); ++ u8 flagreg; ++ u8 ctrl; ++ int err; ++ ++ //get the current ctrl settings ++ ctrl = rx8010->ctrlreg; ++ ++ if (enabled) ++ { ++ if ( rx8010->rtc->uie_rtctimer.enabled ) ++ ctrl |= RX8010_BIT_CTRL_UIE; //set update interrupt enable ++ if ( rx8010->rtc->aie_timer.enabled ) ++ ctrl |= (RX8010_BIT_CTRL_AIE | RX8010_BIT_CTRL_UIE); //set alarm interrupt enable ++ } ++ else ++ { ++ if ( ! rx8010->rtc->uie_rtctimer.enabled ) ++ ctrl &= ~RX8010_BIT_CTRL_UIE; //clear update interrupt enable ++ if ( ! rx8010->rtc->aie_timer.enabled ) ++ { ++ if ( rx8010->rtc->uie_rtctimer.enabled ) ++ ctrl &= ~RX8010_BIT_CTRL_AIE; ++ else ++ ctrl &= ~(RX8010_BIT_CTRL_AIE | RX8010_BIT_CTRL_UIE); //clear alarm interrupt enable ++ } ++ } ++ ++ //clear alarm flag ++ err = rx8010_read_reg(client, RX8010_REG_FLAG, &flagreg); ++ if (err <0) ++ return err; ++ flagreg &= ~RX8010_BIT_FLAG_AF; ++ err = rx8010_write_reg(rx8010->client, RX8010_REG_FLAG, flagreg); ++ if (err) ++ return err; ++ ++ //update the Control register if the setting changed ++ if (ctrl != rx8010->ctrlreg) { ++ rx8010->ctrlreg = ctrl; ++ err = rx8010_write_reg(rx8010->client, RX8010_REG_CTRL, rx8010->ctrlreg); ++ if (err) ++ return err; ++ } ++ ++ return 0; ++} ++ ++//--------------------------------------------------------------------------- ++// rx8010_ioctl() ++// ++//--------------------------------------------------------------------------- ++static int rx8010_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) ++{ ++ struct i2c_client *client = to_i2c_client(dev); ++ //struct rx8010_data *rx8010 = dev_get_drvdata(dev); ++ //struct mutex *lock = &rx8010->rtc->ops_lock; ++ int ret = 0; ++ int tmp; ++ void __user *argp = (void __user *)arg; ++ reg_data reg; ++ ++ dev_dbg(dev, "%s: cmd=%x\n", __func__, cmd); ++ ++ switch (cmd) { ++ case SE_RTC_REG_READ: ++ if (copy_from_user(®, argp, sizeof(reg))) ++ return -EFAULT; ++ if ( reg.number < RX8010_REG_SEC || reg.number > RX8010_REG_IRQ ) ++ return -EFAULT; ++ //mutex_lock(lock); ++ ret = rx8010_read_reg(client, reg.number, ®.value); ++ //mutex_unlock(lock); ++ if (! ret ) ++ return copy_to_user(argp, ®, sizeof(reg)) ? -EFAULT : 0; ++ break; ++ ++ case SE_RTC_REG_WRITE: ++ if (copy_from_user(®, argp, sizeof(reg))) ++ return -EFAULT; ++ if ( reg.number < RX8010_REG_SEC || reg.number > RX8010_REG_IRQ ) ++ return -EFAULT; ++ //mutex_lock(lock); ++ ret = rx8010_write_reg(client, reg.number, reg.value); ++ //mutex_unlock(lock); ++ break; ++ ++ case RTC_VL_READ: ++ //mutex_lock(lock); ++ ret = rx8010_read_reg(client, RX8010_REG_FLAG, ®.value); ++ //mutex_unlock(lock); ++ if (! ret) ++ { ++ tmp = !!(reg.value & RX8010_BIT_FLAG_VLF); ++ return copy_to_user(argp, &tmp, sizeof(tmp)) ? -EFAULT : 0; ++ } ++ break; ++ ++ case RTC_VL_CLR: ++ //mutex_lock(lock); ++ ret = rx8010_read_reg(client, RX8010_REG_FLAG, ®.value); ++ if (! ret) ++ { ++ reg.value &= ~RX8010_BIT_FLAG_VLF; ++ ret = rx8010_write_reg(client, RX8010_REG_FLAG, reg.value); ++ } ++ //mutex_unlock(lock); ++ break; ++ ++ default: ++ return -ENOIOCTLCMD; ++ } ++ ++ return ret; ++} ++ ++static struct rtc_class_ops rx8010_rtc_ops = { ++ .read_time = rx8010_get_time, ++ .set_time = rx8010_set_time, ++ .read_alarm = rx8010_read_alarm, ++ .set_alarm = rx8010_set_alarm, ++ .alarm_irq_enable = rx8010_alarm_irq_enable, ++ .ioctl = rx8010_ioctl, ++}; ++ ++//---------------------------------------------------------------------- ++// rx8010_probe() ++// probe routine for the rx8010 driver ++// ++//---------------------------------------------------------------------- ++static int rx8010_probe(struct i2c_client *client, const struct i2c_device_id *id) ++{ ++ struct device_node *np = client->dev.of_node; ++ struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); ++ struct rx8010_data *rx8010; ++ int err, gpio, i, irqs_success = 0, need_reset = 0; ++ const char * irq_name[2] = {"rx8010-irq_1", "rx8010-irq_2"}; ++ ++ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK)) { ++ dev_err(&adapter->dev, "doesn't support required functionality\n"); ++ err = -EIO; ++ goto errout; ++ } ++ ++ rx8010 = devm_kzalloc(&client->dev, sizeof(struct rx8010_data), GFP_KERNEL); ++ if (!rx8010) { ++ dev_err(&adapter->dev, "failed to alloc memory\n"); ++ err = -ENOMEM; ++ goto errout; ++ } ++ ++ rx8010->client = client; ++ i2c_set_clientdata(client, rx8010); ++ ++ err = rx8010_init_client(client, &need_reset); ++ if (err) ++ goto errout; ++ ++ ++ if (need_reset) { ++ struct rtc_time tm; ++ rtc_time_to_tm(0, &tm); // set to 1970/1/1 ++ rx8010_set_time(&client->dev, &tm); ++ dev_warn(&client->dev, " - time reset to 1970/1/1\n"); ++ } ++ ++ rx8010->rtc = rtc_device_register(client->name, &client->dev, &rx8010_rtc_ops, THIS_MODULE); ++ ++ if (IS_ERR(rx8010->rtc)) { ++ err = PTR_ERR(rx8010->rtc); ++ dev_err(&client->dev, "unable to register the class device\n"); ++ goto errout; ++ } ++ ++ // get interrupts ++ rx8010->irq_1 = rx8010->irq_2 = -1; ++ for ( i=0; i < 2; i++ ) ++ { ++ gpio = of_get_named_gpio(np, irq_name[i], 0); ++ if (gpio_is_valid(gpio)) { ++ int irq; ++ err = devm_gpio_request_one(&client->dev, gpio, GPIOF_DIR_IN, ++ irq_name[i]); ++ if (err) { ++ dev_err(&client->dev, "cannot request %s\n", irq_name[i]); ++ goto errout_reg; ++ } ++ irq = gpio_to_irq(gpio); ++ dev_dbg(&client->dev, "%s %d\n", irq_name[i], irq); ++ if (irq <= 0) { ++ dev_warn(&client->dev, "Failed to " ++ "convert gpio #%d to %s\n", ++ gpio, irq_name[i]); ++ goto errout_reg; ++ } ++ err = devm_request_threaded_irq(&client->dev,irq, NULL, ++ i==0 ? rx8010_irq_1 : rx8010_irq_2, ++ IRQF_TRIGGER_LOW | IRQF_ONESHOT, ++ irq_name[i], ++ client); ++ if (err) { ++ dev_err(&client->dev, "unable to request %s\n", irq_name[i]); ++ goto errout_reg; ++ } ++ if (i == 0) ++ { ++ rx8010->irq_1 = irq; ++ INIT_WORK(&rx8010->work_1, rx8010_work_1); ++ } ++ else ++ { ++ rx8010->irq_2 = irq; ++ INIT_WORK(&rx8010->work_2, rx8010_work_2); ++ } ++ irqs_success++; ++ } else { ++ dev_warn(&client->dev, "%s missing or invalid\n", ++ irq_name[i]); ++ } ++ } ++ ++ // another irq request try if one failed above ++ if ( ! irqs_success && client->irq > 0 ){ ++ dev_info(&client->dev, "IRQ %d supplied\n", client->irq); ++ err = devm_request_threaded_irq(&client->dev,client->irq, NULL, ++ rx8010_irq_1, ++ IRQF_TRIGGER_LOW | IRQF_ONESHOT, ++ "rx8010", client); ++ ++ if (err) { ++ dev_err(&client->dev, "unable to request IRQ\n"); ++ goto errout_reg; ++ } ++ INIT_WORK(&rx8010->work_1, rx8010_work_1); ++ } ++ ++ ++ rx8010->rtc->irq_freq = 1; ++ rx8010->rtc->max_user_freq = 1; ++ ++ return 0; ++ ++errout_reg: ++ rtc_device_unregister(rx8010->rtc); ++ ++errout: ++ dev_err(&adapter->dev, "probing for rx8010 failed\n"); ++ return err; ++} ++ ++//---------------------------------------------------------------------- ++// rx8010_remove() ++// remove routine for the rx8010 driver ++// ++//---------------------------------------------------------------------- ++static int rx8010_remove(struct i2c_client *client) ++{ ++ struct rx8010_data *rx8010 = i2c_get_clientdata(client); ++ struct mutex *lock = &rx8010->rtc->ops_lock; ++ ++ if (client->irq > 0 || rx8010->irq_1 > 0 || rx8010->irq_2 > 0) { ++ mutex_lock(lock); ++ rx8010->exiting = 1; ++ mutex_unlock(lock); ++ ++ //cancel_work ++ if (rx8010->irq_1 > 0 || client->irq > 0) ++ cancel_work_sync(&rx8010->work_1); ++ if (rx8010->irq_2 > 0) ++ cancel_work_sync(&rx8010->work_2); ++ } ++ ++ rtc_device_unregister(rx8010->rtc); ++ ++ return 0; ++} ++ ++static struct i2c_driver rx8010_driver = { ++ .driver = { ++ .name = "rtc-rx8010", ++ .owner = THIS_MODULE, ++ }, ++ .probe = rx8010_probe, ++ .remove = rx8010_remove, ++ .id_table = rx8010_id, ++}; ++ ++module_i2c_driver(rx8010_driver); ++ ++MODULE_AUTHOR("Dennis Henderson "); ++MODULE_DESCRIPTION("RX-8010 SJ RTC driver"); ++MODULE_LICENSE("GPL"); +-- +2.5.0 + diff --git a/recipes-kernel/linux/linux-ge-3.14/0002-mfd-da9063-Add-support-for-production-silicon-varian.patch b/recipes-kernel/linux/linux-ge-3.14/0002-mfd-da9063-Add-support-for-production-silicon-varian.patch new file mode 100644 index 0000000..1866b02 --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/0002-mfd-da9063-Add-support-for-production-silicon-varian.patch @@ -0,0 +1,101 @@ +From 19c444fc1fcc26077437e3fd5acef9fcf6044b9c Mon Sep 17 00:00:00 2001 +From: "Opensource [Steve Twiss]" +Date: Fri, 14 Feb 2014 14:08:11 +0000 +Subject: [PATCH 02/10] mfd: da9063: Add support for production silicon variant + code + +Add the correct silicon variant code ID (0x5) to the driver. This +new code is the 'production' variant code ID for DA9063. + +This patch will remove the older variant code ID which matches the +pre-production silicon ID (0x3) for the DA9063 chip. + +There is also some small amount of correction done in this patch: +it splits the revision code and correctly names it according to +the hardware specification and moves the dev_info() call before +the variant ID test. + +Signed-off-by: Opensource [Steve Twiss] +Signed-off-by: Lee Jones +--- + drivers/mfd/da9063-core.c | 25 ++++++++++++++----------- + include/linux/mfd/da9063/core.h | 6 +++++- + 2 files changed, 19 insertions(+), 12 deletions(-) + +diff --git a/drivers/mfd/da9063-core.c b/drivers/mfd/da9063-core.c +index 26937cd..e70ae31 100644 +--- a/drivers/mfd/da9063-core.c ++++ b/drivers/mfd/da9063-core.c +@@ -110,7 +110,7 @@ static const struct mfd_cell da9063_devs[] = { + int da9063_device_init(struct da9063 *da9063, unsigned int irq) + { + struct da9063_pdata *pdata = da9063->dev->platform_data; +- int model, revision; ++ int model, variant_id, variant_code; + int ret; + + if (pdata) { +@@ -141,23 +141,26 @@ int da9063_device_init(struct da9063 *da9063, unsigned int irq) + return -ENODEV; + } + +- ret = regmap_read(da9063->regmap, DA9063_REG_CHIP_VARIANT, &revision); ++ ret = regmap_read(da9063->regmap, DA9063_REG_CHIP_VARIANT, &variant_id); + if (ret < 0) { +- dev_err(da9063->dev, "Cannot read chip revision id.\n"); ++ dev_err(da9063->dev, "Cannot read chip variant id.\n"); + return -EIO; + } +- revision >>= DA9063_CHIP_VARIANT_SHIFT; +- if (revision != 3) { +- dev_err(da9063->dev, "Unknown chip revision: %d\n", revision); ++ ++ variant_code = variant_id >> DA9063_CHIP_VARIANT_SHIFT; ++ ++ dev_info(da9063->dev, ++ "Device detected (chip-ID: 0x%02X, var-ID: 0x%02X)\n", ++ model, variant_id); ++ ++ if (variant_code != PMIC_DA9063_BB) { ++ dev_err(da9063->dev, "Unknown chip variant code: 0x%02X\n", ++ variant_code); + return -ENODEV; + } + + da9063->model = model; +- da9063->revision = revision; +- +- dev_info(da9063->dev, +- "Device detected (model-ID: 0x%02X rev-ID: 0x%02X)\n", +- model, revision); ++ da9063->variant_code = variant_code; + + ret = da9063_irq_init(da9063); + if (ret) { +diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h +index 2d2a0af..00a9aac 100644 +--- a/include/linux/mfd/da9063/core.h ++++ b/include/linux/mfd/da9063/core.h +@@ -33,6 +33,10 @@ enum da9063_models { + PMIC_DA9063 = 0x61, + }; + ++enum da9063_variant_codes { ++ PMIC_DA9063_BB = 0x5 ++}; ++ + /* Interrupts */ + enum da9063_irqs { + DA9063_IRQ_ONKEY = 0, +@@ -72,7 +76,7 @@ struct da9063 { + /* Device */ + struct device *dev; + unsigned short model; +- unsigned short revision; ++ unsigned char variant_code; + unsigned int flags; + + /* Control interface */ +-- +2.5.0 + diff --git a/recipes-kernel/linux/linux-ge-3.14/0003-mfd-da9063-Upgrade-of-register-definitions-to-suppor.patch b/recipes-kernel/linux/linux-ge-3.14/0003-mfd-da9063-Upgrade-of-register-definitions-to-suppor.patch new file mode 100644 index 0000000..0e22385 --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/0003-mfd-da9063-Upgrade-of-register-definitions-to-suppor.patch @@ -0,0 +1,257 @@ +From b7085a60a9784fce6e0a01c333f875cc7ee9826d Mon Sep 17 00:00:00 2001 +From: "Opensource [Steve Twiss]" +Date: Thu, 6 Mar 2014 16:40:02 +0000 +Subject: [PATCH 03/10] mfd: da9063: Upgrade of register definitions to support + production silicon + +This patch updates the register definitions for DA9063 to support the +production silicon variant code ID (0x5). These changes are not backwards +compatible with the previous register definitions and can only be used +with the production variant of DA9063. + +Signed-off-by: Opensource [Steve Twiss] +Signed-off-by: Lee Jones +--- + include/linux/mfd/da9063/registers.h | 120 ++++++++++++++++++----------------- + 1 file changed, 62 insertions(+), 58 deletions(-) + +diff --git a/include/linux/mfd/da9063/registers.h b/include/linux/mfd/da9063/registers.h +index 5834813..09a85c6 100644 +--- a/include/linux/mfd/da9063/registers.h ++++ b/include/linux/mfd/da9063/registers.h +@@ -17,11 +17,7 @@ + #define _DA9063_REG_H + + #define DA9063_I2C_PAGE_SEL_SHIFT 1 +- + #define DA9063_EVENT_REG_NUM 4 +-#define DA9210_EVENT_REG_NUM 2 +-#define DA9063_EXT_EVENT_REG_NUM (DA9063_EVENT_REG_NUM + \ +- DA9210_EVENT_REG_NUM) + + /* Page selection I2C or SPI always in the begining of any page. */ + /* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */ +@@ -61,9 +57,9 @@ + #define DA9063_REG_GPIO_10_11 0x1A + #define DA9063_REG_GPIO_12_13 0x1B + #define DA9063_REG_GPIO_14_15 0x1C +-#define DA9063_REG_GPIO_MODE_0_7 0x1D +-#define DA9063_REG_GPIO_MODE_8_15 0x1E +-#define DA9063_REG_GPIO_SWITCH_CONT 0x1F ++#define DA9063_REG_GPIO_MODE0_7 0x1D ++#define DA9063_REG_GPIO_MODE8_15 0x1E ++#define DA9063_REG_SWITCH_CONT 0x1F + + /* Regulator Control Registers */ + #define DA9063_REG_BCORE2_CONT 0x20 +@@ -83,7 +79,7 @@ + #define DA9063_REG_LDO9_CONT 0x2E + #define DA9063_REG_LDO10_CONT 0x2F + #define DA9063_REG_LDO11_CONT 0x30 +-#define DA9063_REG_VIB 0x31 ++#define DA9063_REG_SUPPLIES 0x31 + #define DA9063_REG_DVC_1 0x32 + #define DA9063_REG_DVC_2 0x33 + +@@ -97,9 +93,9 @@ + #define DA9063_REG_ADCIN1_RES 0x3A + #define DA9063_REG_ADCIN2_RES 0x3B + #define DA9063_REG_ADCIN3_RES 0x3C +-#define DA9063_REG_MON1_RES 0x3D +-#define DA9063_REG_MON2_RES 0x3E +-#define DA9063_REG_MON3_RES 0x3F ++#define DA9063_REG_MON_A8_RES 0x3D ++#define DA9063_REG_MON_A9_RES 0x3E ++#define DA9063_REG_MON_A10_RES 0x3F + + /* RTC Calendar and Alarm Registers */ + #define DA9063_REG_COUNT_S 0x40 +@@ -108,15 +104,16 @@ + #define DA9063_REG_COUNT_D 0x43 + #define DA9063_REG_COUNT_MO 0x44 + #define DA9063_REG_COUNT_Y 0x45 +-#define DA9063_REG_ALARM_MI 0x46 +-#define DA9063_REG_ALARM_H 0x47 +-#define DA9063_REG_ALARM_D 0x48 +-#define DA9063_REG_ALARM_MO 0x49 +-#define DA9063_REG_ALARM_Y 0x4A +-#define DA9063_REG_SECOND_A 0x4B +-#define DA9063_REG_SECOND_B 0x4C +-#define DA9063_REG_SECOND_C 0x4D +-#define DA9063_REG_SECOND_D 0x4E ++#define DA9063_REG_ALARM_S 0x46 ++#define DA9063_REG_ALARM_MI 0x47 ++#define DA9063_REG_ALARM_H 0x48 ++#define DA9063_REG_ALARM_D 0x49 ++#define DA9063_REG_ALARM_MO 0x4A ++#define DA9063_REG_ALARM_Y 0x4B ++#define DA9063_REG_SECOND_A 0x4C ++#define DA9063_REG_SECOND_B 0x4D ++#define DA9063_REG_SECOND_C 0x4E ++#define DA9063_REG_SECOND_D 0x4F + + /* Sequencer Control Registers */ + #define DA9063_REG_SEQ 0x81 +@@ -226,35 +223,37 @@ + #define DA9063_REG_CONFIG_J 0x10F + #define DA9063_REG_CONFIG_K 0x110 + #define DA9063_REG_CONFIG_L 0x111 +-#define DA9063_REG_MON_REG_1 0x112 +-#define DA9063_REG_MON_REG_2 0x113 +-#define DA9063_REG_MON_REG_3 0x114 +-#define DA9063_REG_MON_REG_4 0x115 +-#define DA9063_REG_MON_REG_5 0x116 +-#define DA9063_REG_MON_REG_6 0x117 +-#define DA9063_REG_TRIM_CLDR 0x118 +- ++#define DA9063_REG_CONFIG_M 0x112 ++#define DA9063_REG_CONFIG_N 0x113 ++ ++#define DA9063_REG_MON_REG_1 0x114 ++#define DA9063_REG_MON_REG_2 0x115 ++#define DA9063_REG_MON_REG_3 0x116 ++#define DA9063_REG_MON_REG_4 0x117 ++#define DA9063_REG_MON_REG_5 0x11E ++#define DA9063_REG_MON_REG_6 0x11F ++#define DA9063_REG_TRIM_CLDR 0x120 + /* General Purpose Registers */ +-#define DA9063_REG_GP_ID_0 0x119 +-#define DA9063_REG_GP_ID_1 0x11A +-#define DA9063_REG_GP_ID_2 0x11B +-#define DA9063_REG_GP_ID_3 0x11C +-#define DA9063_REG_GP_ID_4 0x11D +-#define DA9063_REG_GP_ID_5 0x11E +-#define DA9063_REG_GP_ID_6 0x11F +-#define DA9063_REG_GP_ID_7 0x120 +-#define DA9063_REG_GP_ID_8 0x121 +-#define DA9063_REG_GP_ID_9 0x122 +-#define DA9063_REG_GP_ID_10 0x123 +-#define DA9063_REG_GP_ID_11 0x124 +-#define DA9063_REG_GP_ID_12 0x125 +-#define DA9063_REG_GP_ID_13 0x126 +-#define DA9063_REG_GP_ID_14 0x127 +-#define DA9063_REG_GP_ID_15 0x128 +-#define DA9063_REG_GP_ID_16 0x129 +-#define DA9063_REG_GP_ID_17 0x12A +-#define DA9063_REG_GP_ID_18 0x12B +-#define DA9063_REG_GP_ID_19 0x12C ++#define DA9063_REG_GP_ID_0 0x121 ++#define DA9063_REG_GP_ID_1 0x122 ++#define DA9063_REG_GP_ID_2 0x123 ++#define DA9063_REG_GP_ID_3 0x124 ++#define DA9063_REG_GP_ID_4 0x125 ++#define DA9063_REG_GP_ID_5 0x126 ++#define DA9063_REG_GP_ID_6 0x127 ++#define DA9063_REG_GP_ID_7 0x128 ++#define DA9063_REG_GP_ID_8 0x129 ++#define DA9063_REG_GP_ID_9 0x12A ++#define DA9063_REG_GP_ID_10 0x12B ++#define DA9063_REG_GP_ID_11 0x12C ++#define DA9063_REG_GP_ID_12 0x12D ++#define DA9063_REG_GP_ID_13 0x12E ++#define DA9063_REG_GP_ID_14 0x12F ++#define DA9063_REG_GP_ID_15 0x130 ++#define DA9063_REG_GP_ID_16 0x131 ++#define DA9063_REG_GP_ID_17 0x132 ++#define DA9063_REG_GP_ID_18 0x133 ++#define DA9063_REG_GP_ID_19 0x134 + + /* Chip ID and variant */ + #define DA9063_REG_CHIP_ID 0x181 +@@ -405,8 +404,10 @@ + /* DA9063_REG_CONTROL_B (addr=0x0F) */ + #define DA9063_CHG_SEL 0x01 + #define DA9063_WATCHDOG_PD 0x02 ++#define DA9063_RESET_BLINKING 0x04 + #define DA9063_NRES_MODE 0x08 + #define DA9063_NONKEY_LOCK 0x10 ++#define DA9063_BUCK_SLOWSTART 0x80 + + /* DA9063_REG_CONTROL_C (addr=0x10) */ + #define DA9063_DEBOUNCING_MASK 0x07 +@@ -466,6 +467,7 @@ + #define DA9063_GPADC_PAUSE 0x02 + #define DA9063_PMIF_DIS 0x04 + #define DA9063_HS2WIRE_DIS 0x08 ++#define DA9063_CLDR_PAUSE 0x10 + #define DA9063_BBAT_DIS 0x20 + #define DA9063_OUT_32K_PAUSE 0x40 + #define DA9063_PMCONT_DIS 0x80 +@@ -660,7 +662,7 @@ + #define DA9063_GPIO15_TYPE_GPO 0x04 + #define DA9063_GPIO15_NO_WAKEUP 0x80 + +-/* DA9063_REG_GPIO_MODE_0_7 (addr=0x1D) */ ++/* DA9063_REG_GPIO_MODE0_7 (addr=0x1D) */ + #define DA9063_GPIO0_MODE 0x01 + #define DA9063_GPIO1_MODE 0x02 + #define DA9063_GPIO2_MODE 0x04 +@@ -670,7 +672,7 @@ + #define DA9063_GPIO6_MODE 0x40 + #define DA9063_GPIO7_MODE 0x80 + +-/* DA9063_REG_GPIO_MODE_8_15 (addr=0x1E) */ ++/* DA9063_REG_GPIO_MODE8_15 (addr=0x1E) */ + #define DA9063_GPIO8_MODE 0x01 + #define DA9063_GPIO9_MODE 0x02 + #define DA9063_GPIO10_MODE 0x04 +@@ -702,12 +704,12 @@ + #define DA9063_SWITCH_SR_5MV 0x10 + #define DA9063_SWITCH_SR_10MV 0x20 + #define DA9063_SWITCH_SR_50MV 0x30 +-#define DA9063_SWITCH_SR_DIS 0x40 ++#define DA9063_CORE_SW_INTERNAL 0x40 + #define DA9063_CP_EN_MODE 0x80 + + /* DA9063_REGL_Bxxxx_CONT common bits (addr=0x20-0x25) */ + #define DA9063_BUCK_EN 0x01 +-#define DA9063_BUCK_GPI_MASK 0x06 ++#define DA9063_BUCK_GPI_MASK 0x06 + #define DA9063_BUCK_GPI_OFF 0x00 + #define DA9063_BUCK_GPI_GPIO1 0x02 + #define DA9063_BUCK_GPI_GPIO2 0x04 +@@ -841,25 +843,27 @@ + #define DA9063_COUNT_YEAR_MASK 0x3F + #define DA9063_MONITOR 0x40 + +-/* DA9063_REG_ALARM_MI (addr=0x46) */ ++/* DA9063_REG_ALARM_S (addr=0x46) */ ++#define DA9063_ALARM_S_MASK 0x3F + #define DA9063_ALARM_STATUS_ALARM 0x80 + #define DA9063_ALARM_STATUS_TICK 0x40 ++/* DA9063_REG_ALARM_MI (addr=0x47) */ + #define DA9063_ALARM_MIN_MASK 0x3F + +-/* DA9063_REG_ALARM_H (addr=0x47) */ ++/* DA9063_REG_ALARM_H (addr=0x48) */ + #define DA9063_ALARM_HOUR_MASK 0x1F + +-/* DA9063_REG_ALARM_D (addr=0x48) */ ++/* DA9063_REG_ALARM_D (addr=0x49) */ + #define DA9063_ALARM_DAY_MASK 0x1F + +-/* DA9063_REG_ALARM_MO (addr=0x49) */ ++/* DA9063_REG_ALARM_MO (addr=0x4A) */ + #define DA9063_TICK_WAKE 0x20 + #define DA9063_TICK_TYPE 0x10 + #define DA9063_TICK_TYPE_SEC 0x00 + #define DA9063_TICK_TYPE_MIN 0x10 + #define DA9063_ALARM_MONTH_MASK 0x0F + +-/* DA9063_REG_ALARM_Y (addr=0x4A) */ ++/* DA9063_REG_ALARM_Y (addr=0x4B) */ + #define DA9063_TICK_ON 0x80 + #define DA9063_ALARM_ON 0x40 + #define DA9063_ALARM_YEAR_MASK 0x3F +@@ -906,7 +910,7 @@ + + /* DA9063_REG_Bxxxx_CFG common bits (addr=0x9D-0xA2) */ + #define DA9063_BUCK_FB_MASK 0x07 +-#define DA9063_BUCK_PD_DIS_SHIFT 5 ++#define DA9063_BUCK_PD_DIS_MASK 0x20 + #define DA9063_BUCK_MODE_MASK 0xC0 + #define DA9063_BUCK_MODE_MANUAL 0x00 + #define DA9063_BUCK_MODE_SLEEP 0x40 +-- +2.5.0 + diff --git a/recipes-kernel/linux/linux-ge-3.14/0004-rtc-da9063-RTC-driver.patch b/recipes-kernel/linux/linux-ge-3.14/0004-rtc-da9063-RTC-driver.patch new file mode 100644 index 0000000..aadc66d --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/0004-rtc-da9063-RTC-driver.patch @@ -0,0 +1,399 @@ +From 8115b46c6de0f3afb6e3cb8746a8729cf59cbf56 Mon Sep 17 00:00:00 2001 +From: "Opensource [Steve Twiss]" +Date: Fri, 6 Jun 2014 14:36:03 -0700 +Subject: [PATCH 04/10] rtc: da9063: RTC driver + +Add the RTC driver for DA9063. + +[akpm@linux-foundation.org: coding-style tweaks] +Signed-off-by: Opensource [Steve Twiss] +Cc: Alessandro Zummo +Cc: Lee Jones +Cc: Mark Brown +Cc: Philipp Zabel +Cc: Samuel Ortiz +Cc: David Dajun Chen +Signed-off-by: Andrew Morton +Signed-off-by: Linus Torvalds +--- + drivers/rtc/Kconfig | 10 ++ + drivers/rtc/Makefile | 1 + + drivers/rtc/rtc-da9063.c | 333 +++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 344 insertions(+) + create mode 100644 drivers/rtc/rtc-da9063.c + +diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig +index 87ed3a3..dbafefe 100644 +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -754,6 +754,16 @@ config RTC_DRV_DA9055 + This driver can also be built as a module. If so, the module + will be called rtc-da9055 + ++config RTC_DRV_DA9063 ++ tristate "Dialog Semiconductor DA9063 RTC" ++ depends on MFD_DA9063 ++ help ++ If you say yes here you will get support for the RTC subsystem ++ of the Dialog Semiconductor DA9063. ++ ++ This driver can also be built as a module. If so, the module ++ will be called "rtc-da9063". ++ + config RTC_DRV_EFI + tristate "EFI RTC" + depends on IA64 +diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile +index 1512f48..715be64 100644 +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -32,6 +32,7 @@ obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o + obj-$(CONFIG_RTC_DRV_COH901331) += rtc-coh901331.o + obj-$(CONFIG_RTC_DRV_DA9052) += rtc-da9052.o + obj-$(CONFIG_RTC_DRV_DA9055) += rtc-da9055.o ++obj-$(CONFIG_RTC_DRV_DA9063) += rtc-da9063.o + obj-$(CONFIG_RTC_DRV_DAVINCI) += rtc-davinci.o + obj-$(CONFIG_RTC_DRV_DM355EVM) += rtc-dm355evm.o + obj-$(CONFIG_RTC_DRV_VRTC) += rtc-mrst.o +diff --git a/drivers/rtc/rtc-da9063.c b/drivers/rtc/rtc-da9063.c +new file mode 100644 +index 0000000..5953930 +--- /dev/null ++++ b/drivers/rtc/rtc-da9063.c +@@ -0,0 +1,333 @@ ++/* rtc-da9063.c - Real time clock device driver for DA9063 ++ * Copyright (C) 2013-14 Dialog Semiconductor Ltd. ++ * ++ * This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU Library General Public ++ * License as published by the Free Software Foundation; either ++ * version 2 of the License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ * Library General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define YEARS_TO_DA9063(year) ((year) - 100) ++#define MONTHS_TO_DA9063(month) ((month) + 1) ++#define YEARS_FROM_DA9063(year) ((year) + 100) ++#define MONTHS_FROM_DA9063(month) ((month) - 1) ++ ++#define RTC_DATA_LEN (DA9063_REG_COUNT_Y - DA9063_REG_COUNT_S + 1) ++#define RTC_SEC 0 ++#define RTC_MIN 1 ++#define RTC_HOUR 2 ++#define RTC_DAY 3 ++#define RTC_MONTH 4 ++#define RTC_YEAR 5 ++ ++struct da9063_rtc { ++ struct rtc_device *rtc_dev; ++ struct da9063 *hw; ++ struct rtc_time alarm_time; ++ bool rtc_sync; ++}; ++ ++static void da9063_data_to_tm(u8 *data, struct rtc_time *tm) ++{ ++ tm->tm_sec = data[RTC_SEC] & DA9063_COUNT_SEC_MASK; ++ tm->tm_min = data[RTC_MIN] & DA9063_COUNT_MIN_MASK; ++ tm->tm_hour = data[RTC_HOUR] & DA9063_COUNT_HOUR_MASK; ++ tm->tm_mday = data[RTC_DAY] & DA9063_COUNT_DAY_MASK; ++ tm->tm_mon = MONTHS_FROM_DA9063(data[RTC_MONTH] & ++ DA9063_COUNT_MONTH_MASK); ++ tm->tm_year = YEARS_FROM_DA9063(data[RTC_YEAR] & ++ DA9063_COUNT_YEAR_MASK); ++} ++ ++static void da9063_tm_to_data(struct rtc_time *tm, u8 *data) ++{ ++ data[RTC_SEC] &= ~DA9063_COUNT_SEC_MASK; ++ data[RTC_SEC] |= tm->tm_sec & DA9063_COUNT_SEC_MASK; ++ ++ data[RTC_MIN] &= ~DA9063_COUNT_MIN_MASK; ++ data[RTC_MIN] |= tm->tm_min & DA9063_COUNT_MIN_MASK; ++ ++ data[RTC_HOUR] &= ~DA9063_COUNT_HOUR_MASK; ++ data[RTC_HOUR] |= tm->tm_hour & DA9063_COUNT_HOUR_MASK; ++ ++ data[RTC_DAY] &= ~DA9063_COUNT_DAY_MASK; ++ data[RTC_DAY] |= tm->tm_mday & DA9063_COUNT_DAY_MASK; ++ ++ data[RTC_MONTH] &= ~DA9063_COUNT_MONTH_MASK; ++ data[RTC_MONTH] |= MONTHS_TO_DA9063(tm->tm_mon) & ++ DA9063_COUNT_MONTH_MASK; ++ ++ data[RTC_YEAR] &= ~DA9063_COUNT_YEAR_MASK; ++ data[RTC_YEAR] |= YEARS_TO_DA9063(tm->tm_year) & ++ DA9063_COUNT_YEAR_MASK; ++} ++ ++static int da9063_rtc_stop_alarm(struct device *dev) ++{ ++ struct da9063_rtc *rtc = dev_get_drvdata(dev); ++ ++ return regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y, ++ DA9063_ALARM_ON, 0); ++} ++ ++static int da9063_rtc_start_alarm(struct device *dev) ++{ ++ struct da9063_rtc *rtc = dev_get_drvdata(dev); ++ ++ return regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y, ++ DA9063_ALARM_ON, DA9063_ALARM_ON); ++} ++ ++static int da9063_rtc_read_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct da9063_rtc *rtc = dev_get_drvdata(dev); ++ unsigned long tm_secs; ++ unsigned long al_secs; ++ u8 data[RTC_DATA_LEN]; ++ int ret; ++ ++ ret = regmap_bulk_read(rtc->hw->regmap, DA9063_REG_COUNT_S, ++ data, RTC_DATA_LEN); ++ if (ret < 0) { ++ dev_err(dev, "Failed to read RTC time data: %d\n", ret); ++ return ret; ++ } ++ ++ if (!(data[RTC_SEC] & DA9063_RTC_READ)) { ++ dev_dbg(dev, "RTC not yet ready to be read by the host\n"); ++ return -EINVAL; ++ } ++ ++ da9063_data_to_tm(data, tm); ++ ++ rtc_tm_to_time(tm, &tm_secs); ++ rtc_tm_to_time(&rtc->alarm_time, &al_secs); ++ ++ /* handle the rtc synchronisation delay */ ++ if (rtc->rtc_sync == true && al_secs - tm_secs == 1) ++ memcpy(tm, &rtc->alarm_time, sizeof(struct rtc_time)); ++ else ++ rtc->rtc_sync = false; ++ ++ return rtc_valid_tm(tm); ++} ++ ++static int da9063_rtc_set_time(struct device *dev, struct rtc_time *tm) ++{ ++ struct da9063_rtc *rtc = dev_get_drvdata(dev); ++ u8 data[RTC_DATA_LEN]; ++ int ret; ++ ++ da9063_tm_to_data(tm, data); ++ ret = regmap_bulk_write(rtc->hw->regmap, DA9063_REG_COUNT_S, ++ data, RTC_DATA_LEN); ++ if (ret < 0) ++ dev_err(dev, "Failed to set RTC time data: %d\n", ret); ++ ++ return ret; ++} ++ ++static int da9063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) ++{ ++ struct da9063_rtc *rtc = dev_get_drvdata(dev); ++ u8 data[RTC_DATA_LEN]; ++ int ret; ++ unsigned int val; ++ ++ ret = regmap_bulk_read(rtc->hw->regmap, DA9063_REG_ALARM_S, ++ &data[RTC_SEC], RTC_DATA_LEN); ++ if (ret < 0) ++ return ret; ++ ++ da9063_data_to_tm(data, &alrm->time); ++ ++ alrm->enabled = !!(data[RTC_YEAR] & DA9063_ALARM_ON); ++ ++ ret = regmap_read(rtc->hw->regmap, DA9063_REG_EVENT_A, &val); ++ if (ret < 0) ++ return ret; ++ ++ if (val & (DA9063_E_ALARM)) ++ alrm->pending = 1; ++ else ++ alrm->pending = 0; ++ ++ return 0; ++} ++ ++static int da9063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) ++{ ++ struct da9063_rtc *rtc = dev_get_drvdata(dev); ++ u8 data[RTC_DATA_LEN]; ++ int ret; ++ ++ da9063_tm_to_data(&alrm->time, data); ++ ++ ret = da9063_rtc_stop_alarm(dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to stop alarm: %d\n", ret); ++ return ret; ++ } ++ ++ ret = regmap_bulk_write(rtc->hw->regmap, DA9063_REG_ALARM_S, ++ data, RTC_DATA_LEN); ++ if (ret < 0) { ++ dev_err(dev, "Failed to write alarm: %d\n", ret); ++ return ret; ++ } ++ ++ rtc->alarm_time = alrm->time; ++ ++ if (alrm->enabled) { ++ ret = da9063_rtc_start_alarm(dev); ++ if (ret < 0) { ++ dev_err(dev, "Failed to start alarm: %d\n", ret); ++ return ret; ++ } ++ } ++ ++ return ret; ++} ++ ++static int da9063_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) ++{ ++ if (enabled) ++ return da9063_rtc_start_alarm(dev); ++ else ++ return da9063_rtc_stop_alarm(dev); ++} ++ ++static irqreturn_t da9063_alarm_event(int irq, void *data) ++{ ++ struct da9063_rtc *rtc = data; ++ ++ regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y, ++ DA9063_ALARM_ON, 0); ++ ++ rtc->rtc_sync = true; ++ rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF); ++ ++ return IRQ_HANDLED; ++} ++ ++static const struct rtc_class_ops da9063_rtc_ops = { ++ .read_time = da9063_rtc_read_time, ++ .set_time = da9063_rtc_set_time, ++ .read_alarm = da9063_rtc_read_alarm, ++ .set_alarm = da9063_rtc_set_alarm, ++ .alarm_irq_enable = da9063_rtc_alarm_irq_enable, ++}; ++ ++static int da9063_rtc_probe(struct platform_device *pdev) ++{ ++ struct da9063 *da9063 = dev_get_drvdata(pdev->dev.parent); ++ struct da9063_rtc *rtc; ++ int irq_alarm; ++ u8 data[RTC_DATA_LEN]; ++ int ret; ++ ++ ret = regmap_update_bits(da9063->regmap, DA9063_REG_CONTROL_E, ++ DA9063_RTC_EN, DA9063_RTC_EN); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to enable RTC\n"); ++ goto err; ++ } ++ ++ ret = regmap_update_bits(da9063->regmap, DA9063_REG_EN_32K, ++ DA9063_CRYSTAL, DA9063_CRYSTAL); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to run 32kHz oscillator\n"); ++ goto err; ++ } ++ ++ ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_S, ++ DA9063_ALARM_STATUS_TICK | DA9063_ALARM_STATUS_ALARM, ++ 0); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to access RTC alarm register\n"); ++ goto err; ++ } ++ ++ ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_S, ++ DA9063_ALARM_STATUS_ALARM, ++ DA9063_ALARM_STATUS_ALARM); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to access RTC alarm register\n"); ++ goto err; ++ } ++ ++ ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_Y, ++ DA9063_TICK_ON, 0); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to disable TICKs\n"); ++ goto err; ++ } ++ ++ ret = regmap_bulk_read(da9063->regmap, DA9063_REG_ALARM_S, ++ data, RTC_DATA_LEN); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Failed to read initial alarm data: %d\n", ++ ret); ++ goto err; ++ } ++ ++ rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); ++ if (!rtc) ++ return -ENOMEM; ++ ++ platform_set_drvdata(pdev, rtc); ++ ++ irq_alarm = platform_get_irq_byname(pdev, "ALARM"); ++ ret = devm_request_threaded_irq(&pdev->dev, irq_alarm, NULL, ++ da9063_alarm_event, ++ IRQF_TRIGGER_LOW | IRQF_ONESHOT, ++ "ALARM", rtc); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to request ALARM IRQ %d: %d\n", ++ irq_alarm, ret); ++ goto err; ++ } ++ ++ rtc->hw = da9063; ++ rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, DA9063_DRVNAME_RTC, ++ &da9063_rtc_ops, THIS_MODULE); ++ if (IS_ERR(rtc->rtc_dev)) ++ return PTR_ERR(rtc->rtc_dev); ++ ++ da9063_data_to_tm(data, &rtc->alarm_time); ++ rtc->rtc_sync = false; ++err: ++ return ret; ++} ++ ++static struct platform_driver da9063_rtc_driver = { ++ .probe = da9063_rtc_probe, ++ .driver = { ++ .name = DA9063_DRVNAME_RTC, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++module_platform_driver(da9063_rtc_driver); ++ ++MODULE_AUTHOR("S Twiss "); ++MODULE_DESCRIPTION("Real time clock device driver for Dialog DA9063"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DA9063_DRVNAME_RTC); +-- +2.5.0 + diff --git a/recipes-kernel/linux/linux-ge-3.14/0005-mfd-da9063-Add-support-for-AD-silicon-variant.patch b/recipes-kernel/linux/linux-ge-3.14/0005-mfd-da9063-Add-support-for-AD-silicon-variant.patch new file mode 100644 index 0000000..0a7e161 --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/0005-mfd-da9063-Add-support-for-AD-silicon-variant.patch @@ -0,0 +1,582 @@ +From bdc0b750279f006abb80a60b288761e9674c51a3 Mon Sep 17 00:00:00 2001 +From: "Opensource [Steve Twiss]" +Date: Mon, 21 Jul 2014 11:39:33 +0100 +Subject: [PATCH 05/10] mfd: da9063: Add support for AD silicon variant + +Add register definitions for DA9063 AD (0x3) silicon variant ID +the ability to choose the silicon variant at run-time using regmap +configuration. This patch also adds RTC support for the AD silicon +changes. + +It adds both BB and AD support as regmap ranges and then makes the +distinction between the two tables at run-time. This allows both AD +and BB silicon variants to be supported at the same time. + +Suggested-by: Philipp Zabel +Signed-off-by: Opensource [Steve Twiss] +Signed-off-by: Lee Jones +--- + drivers/mfd/da9063-core.c | 6 +- + drivers/mfd/da9063-i2c.c | 134 ++++++++++++++++++++++++++++------- + drivers/rtc/rtc-da9063.c | 54 +++++++++----- + include/linux/mfd/da9063/core.h | 3 +- + include/linux/mfd/da9063/registers.h | 129 +++++++++++++++++++++------------ + 5 files changed, 236 insertions(+), 90 deletions(-) + +diff --git a/drivers/mfd/da9063-core.c b/drivers/mfd/da9063-core.c +index e70ae31..93db8bb 100644 +--- a/drivers/mfd/da9063-core.c ++++ b/drivers/mfd/da9063-core.c +@@ -153,9 +153,9 @@ int da9063_device_init(struct da9063 *da9063, unsigned int irq) + "Device detected (chip-ID: 0x%02X, var-ID: 0x%02X)\n", + model, variant_id); + +- if (variant_code != PMIC_DA9063_BB) { +- dev_err(da9063->dev, "Unknown chip variant code: 0x%02X\n", +- variant_code); ++ if (variant_code < PMIC_DA9063_BB && variant_code != PMIC_DA9063_AD) { ++ dev_err(da9063->dev, ++ "Cannot support variant code: 0x%02X\n", variant_code); + return -ENODEV; + } + +diff --git a/drivers/mfd/da9063-i2c.c b/drivers/mfd/da9063-i2c.c +index 8db5c805..21fd8d9 100644 +--- a/drivers/mfd/da9063-i2c.c ++++ b/drivers/mfd/da9063-i2c.c +@@ -25,10 +25,10 @@ + #include + #include + +-static const struct regmap_range da9063_readable_ranges[] = { ++static const struct regmap_range da9063_ad_readable_ranges[] = { + { + .range_min = DA9063_REG_PAGE_CON, +- .range_max = DA9063_REG_SECOND_D, ++ .range_max = DA9063_AD_REG_SECOND_D, + }, { + .range_min = DA9063_REG_SEQ, + .range_max = DA9063_REG_ID_32_31, +@@ -37,14 +37,14 @@ static const struct regmap_range da9063_readable_ranges[] = { + .range_max = DA9063_REG_AUTO3_LOW, + }, { + .range_min = DA9063_REG_T_OFFSET, +- .range_max = DA9063_REG_GP_ID_19, ++ .range_max = DA9063_AD_REG_GP_ID_19, + }, { + .range_min = DA9063_REG_CHIP_ID, + .range_max = DA9063_REG_CHIP_VARIANT, + }, + }; + +-static const struct regmap_range da9063_writeable_ranges[] = { ++static const struct regmap_range da9063_ad_writeable_ranges[] = { + { + .range_min = DA9063_REG_PAGE_CON, + .range_max = DA9063_REG_PAGE_CON, +@@ -53,7 +53,7 @@ static const struct regmap_range da9063_writeable_ranges[] = { + .range_max = DA9063_REG_VSYS_MON, + }, { + .range_min = DA9063_REG_COUNT_S, +- .range_max = DA9063_REG_ALARM_Y, ++ .range_max = DA9063_AD_REG_ALARM_Y, + }, { + .range_min = DA9063_REG_SEQ, + .range_max = DA9063_REG_ID_32_31, +@@ -62,14 +62,14 @@ static const struct regmap_range da9063_writeable_ranges[] = { + .range_max = DA9063_REG_AUTO3_LOW, + }, { + .range_min = DA9063_REG_CONFIG_I, +- .range_max = DA9063_REG_MON_REG_4, ++ .range_max = DA9063_AD_REG_MON_REG_4, + }, { +- .range_min = DA9063_REG_GP_ID_0, +- .range_max = DA9063_REG_GP_ID_19, ++ .range_min = DA9063_AD_REG_GP_ID_0, ++ .range_max = DA9063_AD_REG_GP_ID_19, + }, + }; + +-static const struct regmap_range da9063_volatile_ranges[] = { ++static const struct regmap_range da9063_ad_volatile_ranges[] = { + { + .range_min = DA9063_REG_STATUS_A, + .range_max = DA9063_REG_EVENT_D, +@@ -81,26 +81,104 @@ static const struct regmap_range da9063_volatile_ranges[] = { + .range_max = DA9063_REG_ADC_MAN, + }, { + .range_min = DA9063_REG_ADC_RES_L, +- .range_max = DA9063_REG_SECOND_D, ++ .range_max = DA9063_AD_REG_SECOND_D, + }, { +- .range_min = DA9063_REG_MON_REG_5, +- .range_max = DA9063_REG_MON_REG_6, ++ .range_min = DA9063_AD_REG_MON_REG_5, ++ .range_max = DA9063_AD_REG_MON_REG_6, + }, + }; + +-static const struct regmap_access_table da9063_readable_table = { +- .yes_ranges = da9063_readable_ranges, +- .n_yes_ranges = ARRAY_SIZE(da9063_readable_ranges), ++static const struct regmap_access_table da9063_ad_readable_table = { ++ .yes_ranges = da9063_ad_readable_ranges, ++ .n_yes_ranges = ARRAY_SIZE(da9063_ad_readable_ranges), + }; + +-static const struct regmap_access_table da9063_writeable_table = { +- .yes_ranges = da9063_writeable_ranges, +- .n_yes_ranges = ARRAY_SIZE(da9063_writeable_ranges), ++static const struct regmap_access_table da9063_ad_writeable_table = { ++ .yes_ranges = da9063_ad_writeable_ranges, ++ .n_yes_ranges = ARRAY_SIZE(da9063_ad_writeable_ranges), + }; + +-static const struct regmap_access_table da9063_volatile_table = { +- .yes_ranges = da9063_volatile_ranges, +- .n_yes_ranges = ARRAY_SIZE(da9063_volatile_ranges), ++static const struct regmap_access_table da9063_ad_volatile_table = { ++ .yes_ranges = da9063_ad_volatile_ranges, ++ .n_yes_ranges = ARRAY_SIZE(da9063_ad_volatile_ranges), ++}; ++ ++static const struct regmap_range da9063_bb_readable_ranges[] = { ++ { ++ .range_min = DA9063_REG_PAGE_CON, ++ .range_max = DA9063_BB_REG_SECOND_D, ++ }, { ++ .range_min = DA9063_REG_SEQ, ++ .range_max = DA9063_REG_ID_32_31, ++ }, { ++ .range_min = DA9063_REG_SEQ_A, ++ .range_max = DA9063_REG_AUTO3_LOW, ++ }, { ++ .range_min = DA9063_REG_T_OFFSET, ++ .range_max = DA9063_BB_REG_GP_ID_19, ++ }, { ++ .range_min = DA9063_REG_CHIP_ID, ++ .range_max = DA9063_REG_CHIP_VARIANT, ++ }, ++}; ++ ++static const struct regmap_range da9063_bb_writeable_ranges[] = { ++ { ++ .range_min = DA9063_REG_PAGE_CON, ++ .range_max = DA9063_REG_PAGE_CON, ++ }, { ++ .range_min = DA9063_REG_FAULT_LOG, ++ .range_max = DA9063_REG_VSYS_MON, ++ }, { ++ .range_min = DA9063_REG_COUNT_S, ++ .range_max = DA9063_BB_REG_ALARM_Y, ++ }, { ++ .range_min = DA9063_REG_SEQ, ++ .range_max = DA9063_REG_ID_32_31, ++ }, { ++ .range_min = DA9063_REG_SEQ_A, ++ .range_max = DA9063_REG_AUTO3_LOW, ++ }, { ++ .range_min = DA9063_REG_CONFIG_I, ++ .range_max = DA9063_BB_REG_MON_REG_4, ++ }, { ++ .range_min = DA9063_BB_REG_GP_ID_0, ++ .range_max = DA9063_BB_REG_GP_ID_19, ++ }, ++}; ++ ++static const struct regmap_range da9063_bb_volatile_ranges[] = { ++ { ++ .range_min = DA9063_REG_STATUS_A, ++ .range_max = DA9063_REG_EVENT_D, ++ }, { ++ .range_min = DA9063_REG_CONTROL_F, ++ .range_max = DA9063_REG_CONTROL_F, ++ }, { ++ .range_min = DA9063_REG_ADC_MAN, ++ .range_max = DA9063_REG_ADC_MAN, ++ }, { ++ .range_min = DA9063_REG_ADC_RES_L, ++ .range_max = DA9063_BB_REG_SECOND_D, ++ }, { ++ .range_min = DA9063_BB_REG_MON_REG_5, ++ .range_max = DA9063_BB_REG_MON_REG_6, ++ }, ++}; ++ ++static const struct regmap_access_table da9063_bb_readable_table = { ++ .yes_ranges = da9063_bb_readable_ranges, ++ .n_yes_ranges = ARRAY_SIZE(da9063_bb_readable_ranges), ++}; ++ ++static const struct regmap_access_table da9063_bb_writeable_table = { ++ .yes_ranges = da9063_bb_writeable_ranges, ++ .n_yes_ranges = ARRAY_SIZE(da9063_bb_writeable_ranges), ++}; ++ ++static const struct regmap_access_table da9063_bb_volatile_table = { ++ .yes_ranges = da9063_bb_volatile_ranges, ++ .n_yes_ranges = ARRAY_SIZE(da9063_bb_volatile_ranges), + }; + + static const struct regmap_range_cfg da9063_range_cfg[] = { +@@ -123,10 +201,6 @@ static struct regmap_config da9063_regmap_config = { + .max_register = DA9063_REG_CHIP_VARIANT, + + .cache_type = REGCACHE_RBTREE, +- +- .rd_table = &da9063_readable_table, +- .wr_table = &da9063_writeable_table, +- .volatile_table = &da9063_volatile_table, + }; + + static int da9063_i2c_probe(struct i2c_client *i2c, +@@ -143,6 +217,16 @@ static int da9063_i2c_probe(struct i2c_client *i2c, + da9063->dev = &i2c->dev; + da9063->chip_irq = i2c->irq; + ++ if (da9063->variant_code == PMIC_DA9063_AD) { ++ da9063_regmap_config.rd_table = &da9063_ad_readable_table; ++ da9063_regmap_config.wr_table = &da9063_ad_writeable_table; ++ da9063_regmap_config.volatile_table = &da9063_ad_volatile_table; ++ } else { ++ da9063_regmap_config.rd_table = &da9063_bb_readable_table; ++ da9063_regmap_config.wr_table = &da9063_bb_writeable_table; ++ da9063_regmap_config.volatile_table = &da9063_bb_volatile_table; ++ } ++ + da9063->regmap = devm_regmap_init_i2c(i2c, &da9063_regmap_config); + if (IS_ERR(da9063->regmap)) { + ret = PTR_ERR(da9063->regmap); +diff --git a/drivers/rtc/rtc-da9063.c b/drivers/rtc/rtc-da9063.c +index 5953930..731ed1a 100644 +--- a/drivers/rtc/rtc-da9063.c ++++ b/drivers/rtc/rtc-da9063.c +@@ -29,6 +29,8 @@ + #define YEARS_FROM_DA9063(year) ((year) + 100) + #define MONTHS_FROM_DA9063(month) ((month) - 1) + ++#define RTC_ALARM_DATA_LEN (DA9063_AD_REG_ALARM_Y - DA9063_AD_REG_ALARM_MI + 1) ++ + #define RTC_DATA_LEN (DA9063_REG_COUNT_Y - DA9063_REG_COUNT_S + 1) + #define RTC_SEC 0 + #define RTC_MIN 1 +@@ -42,6 +44,10 @@ struct da9063_rtc { + struct da9063 *hw; + struct rtc_time alarm_time; + bool rtc_sync; ++ int alarm_year; ++ int alarm_start; ++ int alarm_len; ++ int data_start; + }; + + static void da9063_data_to_tm(u8 *data, struct rtc_time *tm) +@@ -83,7 +89,7 @@ static int da9063_rtc_stop_alarm(struct device *dev) + { + struct da9063_rtc *rtc = dev_get_drvdata(dev); + +- return regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y, ++ return regmap_update_bits(rtc->hw->regmap, rtc->alarm_year, + DA9063_ALARM_ON, 0); + } + +@@ -91,7 +97,7 @@ static int da9063_rtc_start_alarm(struct device *dev) + { + struct da9063_rtc *rtc = dev_get_drvdata(dev); + +- return regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y, ++ return regmap_update_bits(rtc->hw->regmap, rtc->alarm_year, + DA9063_ALARM_ON, DA9063_ALARM_ON); + } + +@@ -151,8 +157,9 @@ static int da9063_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm) + int ret; + unsigned int val; + +- ret = regmap_bulk_read(rtc->hw->regmap, DA9063_REG_ALARM_S, +- &data[RTC_SEC], RTC_DATA_LEN); ++ data[RTC_SEC] = 0; ++ ret = regmap_bulk_read(rtc->hw->regmap, rtc->alarm_start, ++ &data[rtc->data_start], rtc->alarm_len); + if (ret < 0) + return ret; + +@@ -186,14 +193,14 @@ static int da9063_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) + return ret; + } + +- ret = regmap_bulk_write(rtc->hw->regmap, DA9063_REG_ALARM_S, +- data, RTC_DATA_LEN); ++ ret = regmap_bulk_write(rtc->hw->regmap, rtc->alarm_start, ++ &data[rtc->data_start], rtc->alarm_len); + if (ret < 0) { + dev_err(dev, "Failed to write alarm: %d\n", ret); + return ret; + } + +- rtc->alarm_time = alrm->time; ++ da9063_data_to_tm(data, &rtc->alarm_time); + + if (alrm->enabled) { + ret = da9063_rtc_start_alarm(dev); +@@ -218,7 +225,7 @@ static irqreturn_t da9063_alarm_event(int irq, void *data) + { + struct da9063_rtc *rtc = data; + +- regmap_update_bits(rtc->hw->regmap, DA9063_REG_ALARM_Y, ++ regmap_update_bits(rtc->hw->regmap, rtc->alarm_year, + DA9063_ALARM_ON, 0); + + rtc->rtc_sync = true; +@@ -257,7 +264,23 @@ static int da9063_rtc_probe(struct platform_device *pdev) + goto err; + } + +- ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_S, ++ rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); ++ if (!rtc) ++ return -ENOMEM; ++ ++ if (da9063->variant_code == PMIC_DA9063_AD) { ++ rtc->alarm_year = DA9063_AD_REG_ALARM_Y; ++ rtc->alarm_start = DA9063_AD_REG_ALARM_MI; ++ rtc->alarm_len = RTC_ALARM_DATA_LEN; ++ rtc->data_start = RTC_MIN; ++ } else { ++ rtc->alarm_year = DA9063_BB_REG_ALARM_Y; ++ rtc->alarm_start = DA9063_BB_REG_ALARM_S; ++ rtc->alarm_len = RTC_DATA_LEN; ++ rtc->data_start = RTC_SEC; ++ } ++ ++ ret = regmap_update_bits(da9063->regmap, rtc->alarm_start, + DA9063_ALARM_STATUS_TICK | DA9063_ALARM_STATUS_ALARM, + 0); + if (ret < 0) { +@@ -265,7 +288,7 @@ static int da9063_rtc_probe(struct platform_device *pdev) + goto err; + } + +- ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_S, ++ ret = regmap_update_bits(da9063->regmap, rtc->alarm_start, + DA9063_ALARM_STATUS_ALARM, + DA9063_ALARM_STATUS_ALARM); + if (ret < 0) { +@@ -273,25 +296,22 @@ static int da9063_rtc_probe(struct platform_device *pdev) + goto err; + } + +- ret = regmap_update_bits(da9063->regmap, DA9063_REG_ALARM_Y, ++ ret = regmap_update_bits(da9063->regmap, rtc->alarm_year, + DA9063_TICK_ON, 0); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to disable TICKs\n"); + goto err; + } + +- ret = regmap_bulk_read(da9063->regmap, DA9063_REG_ALARM_S, +- data, RTC_DATA_LEN); ++ data[RTC_SEC] = 0; ++ ret = regmap_bulk_read(da9063->regmap, rtc->alarm_start, ++ &data[rtc->data_start], rtc->alarm_len); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to read initial alarm data: %d\n", + ret); + goto err; + } + +- rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); +- if (!rtc) +- return -ENOMEM; +- + platform_set_drvdata(pdev, rtc); + + irq_alarm = platform_get_irq_byname(pdev, "ALARM"); +diff --git a/include/linux/mfd/da9063/core.h b/include/linux/mfd/da9063/core.h +index 00a9aac..b92a326 100644 +--- a/include/linux/mfd/da9063/core.h ++++ b/include/linux/mfd/da9063/core.h +@@ -34,7 +34,8 @@ enum da9063_models { + }; + + enum da9063_variant_codes { +- PMIC_DA9063_BB = 0x5 ++ PMIC_DA9063_AD = 0x3, ++ PMIC_DA9063_BB = 0x5, + }; + + /* Interrupts */ +diff --git a/include/linux/mfd/da9063/registers.h b/include/linux/mfd/da9063/registers.h +index 09a85c6..2e0ba6d5 100644 +--- a/include/linux/mfd/da9063/registers.h ++++ b/include/linux/mfd/da9063/registers.h +@@ -104,16 +104,27 @@ + #define DA9063_REG_COUNT_D 0x43 + #define DA9063_REG_COUNT_MO 0x44 + #define DA9063_REG_COUNT_Y 0x45 +-#define DA9063_REG_ALARM_S 0x46 +-#define DA9063_REG_ALARM_MI 0x47 +-#define DA9063_REG_ALARM_H 0x48 +-#define DA9063_REG_ALARM_D 0x49 +-#define DA9063_REG_ALARM_MO 0x4A +-#define DA9063_REG_ALARM_Y 0x4B +-#define DA9063_REG_SECOND_A 0x4C +-#define DA9063_REG_SECOND_B 0x4D +-#define DA9063_REG_SECOND_C 0x4E +-#define DA9063_REG_SECOND_D 0x4F ++ ++#define DA9063_AD_REG_ALARM_MI 0x46 ++#define DA9063_AD_REG_ALARM_H 0x47 ++#define DA9063_AD_REG_ALARM_D 0x48 ++#define DA9063_AD_REG_ALARM_MO 0x49 ++#define DA9063_AD_REG_ALARM_Y 0x4A ++#define DA9063_AD_REG_SECOND_A 0x4B ++#define DA9063_AD_REG_SECOND_B 0x4C ++#define DA9063_AD_REG_SECOND_C 0x4D ++#define DA9063_AD_REG_SECOND_D 0x4E ++ ++#define DA9063_BB_REG_ALARM_S 0x46 ++#define DA9063_BB_REG_ALARM_MI 0x47 ++#define DA9063_BB_REG_ALARM_H 0x48 ++#define DA9063_BB_REG_ALARM_D 0x49 ++#define DA9063_BB_REG_ALARM_MO 0x4A ++#define DA9063_BB_REG_ALARM_Y 0x4B ++#define DA9063_BB_REG_SECOND_A 0x4C ++#define DA9063_BB_REG_SECOND_B 0x4D ++#define DA9063_BB_REG_SECOND_C 0x4E ++#define DA9063_BB_REG_SECOND_D 0x4F + + /* Sequencer Control Registers */ + #define DA9063_REG_SEQ 0x81 +@@ -223,37 +234,67 @@ + #define DA9063_REG_CONFIG_J 0x10F + #define DA9063_REG_CONFIG_K 0x110 + #define DA9063_REG_CONFIG_L 0x111 +-#define DA9063_REG_CONFIG_M 0x112 +-#define DA9063_REG_CONFIG_N 0x113 +- +-#define DA9063_REG_MON_REG_1 0x114 +-#define DA9063_REG_MON_REG_2 0x115 +-#define DA9063_REG_MON_REG_3 0x116 +-#define DA9063_REG_MON_REG_4 0x117 +-#define DA9063_REG_MON_REG_5 0x11E +-#define DA9063_REG_MON_REG_6 0x11F +-#define DA9063_REG_TRIM_CLDR 0x120 ++ ++#define DA9063_AD_REG_MON_REG_1 0x112 ++#define DA9063_AD_REG_MON_REG_2 0x113 ++#define DA9063_AD_REG_MON_REG_3 0x114 ++#define DA9063_AD_REG_MON_REG_4 0x115 ++#define DA9063_AD_REG_MON_REG_5 0x116 ++#define DA9063_AD_REG_MON_REG_6 0x117 ++#define DA9063_AD_REG_TRIM_CLDR 0x118 ++ ++#define DA9063_AD_REG_GP_ID_0 0x119 ++#define DA9063_AD_REG_GP_ID_1 0x11A ++#define DA9063_AD_REG_GP_ID_2 0x11B ++#define DA9063_AD_REG_GP_ID_3 0x11C ++#define DA9063_AD_REG_GP_ID_4 0x11D ++#define DA9063_AD_REG_GP_ID_5 0x11E ++#define DA9063_AD_REG_GP_ID_6 0x11F ++#define DA9063_AD_REG_GP_ID_7 0x120 ++#define DA9063_AD_REG_GP_ID_8 0x121 ++#define DA9063_AD_REG_GP_ID_9 0x122 ++#define DA9063_AD_REG_GP_ID_10 0x123 ++#define DA9063_AD_REG_GP_ID_11 0x124 ++#define DA9063_AD_REG_GP_ID_12 0x125 ++#define DA9063_AD_REG_GP_ID_13 0x126 ++#define DA9063_AD_REG_GP_ID_14 0x127 ++#define DA9063_AD_REG_GP_ID_15 0x128 ++#define DA9063_AD_REG_GP_ID_16 0x129 ++#define DA9063_AD_REG_GP_ID_17 0x12A ++#define DA9063_AD_REG_GP_ID_18 0x12B ++#define DA9063_AD_REG_GP_ID_19 0x12C ++ ++#define DA9063_BB_REG_CONFIG_M 0x112 ++#define DA9063_BB_REG_CONFIG_N 0x113 ++ ++#define DA9063_BB_REG_MON_REG_1 0x114 ++#define DA9063_BB_REG_MON_REG_2 0x115 ++#define DA9063_BB_REG_MON_REG_3 0x116 ++#define DA9063_BB_REG_MON_REG_4 0x117 ++#define DA9063_BB_REG_MON_REG_5 0x11E ++#define DA9063_BB_REG_MON_REG_6 0x11F ++#define DA9063_BB_REG_TRIM_CLDR 0x120 + /* General Purpose Registers */ +-#define DA9063_REG_GP_ID_0 0x121 +-#define DA9063_REG_GP_ID_1 0x122 +-#define DA9063_REG_GP_ID_2 0x123 +-#define DA9063_REG_GP_ID_3 0x124 +-#define DA9063_REG_GP_ID_4 0x125 +-#define DA9063_REG_GP_ID_5 0x126 +-#define DA9063_REG_GP_ID_6 0x127 +-#define DA9063_REG_GP_ID_7 0x128 +-#define DA9063_REG_GP_ID_8 0x129 +-#define DA9063_REG_GP_ID_9 0x12A +-#define DA9063_REG_GP_ID_10 0x12B +-#define DA9063_REG_GP_ID_11 0x12C +-#define DA9063_REG_GP_ID_12 0x12D +-#define DA9063_REG_GP_ID_13 0x12E +-#define DA9063_REG_GP_ID_14 0x12F +-#define DA9063_REG_GP_ID_15 0x130 +-#define DA9063_REG_GP_ID_16 0x131 +-#define DA9063_REG_GP_ID_17 0x132 +-#define DA9063_REG_GP_ID_18 0x133 +-#define DA9063_REG_GP_ID_19 0x134 ++#define DA9063_BB_REG_GP_ID_0 0x121 ++#define DA9063_BB_REG_GP_ID_1 0x122 ++#define DA9063_BB_REG_GP_ID_2 0x123 ++#define DA9063_BB_REG_GP_ID_3 0x124 ++#define DA9063_BB_REG_GP_ID_4 0x125 ++#define DA9063_BB_REG_GP_ID_5 0x126 ++#define DA9063_BB_REG_GP_ID_6 0x127 ++#define DA9063_BB_REG_GP_ID_7 0x128 ++#define DA9063_BB_REG_GP_ID_8 0x129 ++#define DA9063_BB_REG_GP_ID_9 0x12A ++#define DA9063_BB_REG_GP_ID_10 0x12B ++#define DA9063_BB_REG_GP_ID_11 0x12C ++#define DA9063_BB_REG_GP_ID_12 0x12D ++#define DA9063_BB_REG_GP_ID_13 0x12E ++#define DA9063_BB_REG_GP_ID_14 0x12F ++#define DA9063_BB_REG_GP_ID_15 0x130 ++#define DA9063_BB_REG_GP_ID_16 0x131 ++#define DA9063_BB_REG_GP_ID_17 0x132 ++#define DA9063_BB_REG_GP_ID_18 0x133 ++#define DA9063_BB_REG_GP_ID_19 0x134 + + /* Chip ID and variant */ + #define DA9063_REG_CHIP_ID 0x181 +@@ -404,10 +445,10 @@ + /* DA9063_REG_CONTROL_B (addr=0x0F) */ + #define DA9063_CHG_SEL 0x01 + #define DA9063_WATCHDOG_PD 0x02 +-#define DA9063_RESET_BLINKING 0x04 ++#define DA9063_BB_RESET_BLINKING 0x04 + #define DA9063_NRES_MODE 0x08 + #define DA9063_NONKEY_LOCK 0x10 +-#define DA9063_BUCK_SLOWSTART 0x80 ++#define DA9063_BB_BUCK_SLOWSTART 0x80 + + /* DA9063_REG_CONTROL_C (addr=0x10) */ + #define DA9063_DEBOUNCING_MASK 0x07 +@@ -467,7 +508,7 @@ + #define DA9063_GPADC_PAUSE 0x02 + #define DA9063_PMIF_DIS 0x04 + #define DA9063_HS2WIRE_DIS 0x08 +-#define DA9063_CLDR_PAUSE 0x10 ++#define DA9063_BB_CLDR_PAUSE 0x10 + #define DA9063_BBAT_DIS 0x20 + #define DA9063_OUT_32K_PAUSE 0x40 + #define DA9063_PMCONT_DIS 0x80 +@@ -844,7 +885,7 @@ + #define DA9063_MONITOR 0x40 + + /* DA9063_REG_ALARM_S (addr=0x46) */ +-#define DA9063_ALARM_S_MASK 0x3F ++#define DA9063_BB_ALARM_S_MASK 0x3F + #define DA9063_ALARM_STATUS_ALARM 0x80 + #define DA9063_ALARM_STATUS_TICK 0x40 + /* DA9063_REG_ALARM_MI (addr=0x47) */ +-- +2.5.0 + diff --git a/recipes-kernel/linux/linux-ge-3.14/0006-mfd-da9063-Get-irq-base-dynamically-before-registeri.patch b/recipes-kernel/linux/linux-ge-3.14/0006-mfd-da9063-Get-irq-base-dynamically-before-registeri.patch new file mode 100644 index 0000000..4870138 --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/0006-mfd-da9063-Get-irq-base-dynamically-before-registeri.patch @@ -0,0 +1,42 @@ +From f996ed516921512ab7a13db776f66420e07e6b90 Mon Sep 17 00:00:00 2001 +From: Dmitry Lavnikevich +Date: Fri, 21 Nov 2014 18:29:07 +0300 +Subject: [PATCH 06/10] mfd: da9063: Get irq base dynamically before + registering device + +After registering mfd device with proper irq_base +platform_get_irq_byname() calls will return VIRQ instead of local IRQ. +This fixes da9063 rtc registration issue: +da9063-rtc da9063-rtc: Failed to request ALARM IRQ 1: -22 + +Signed-off-by: Dmitry Lavnikevich +Signed-off-by: Lee Jones +--- + drivers/mfd/da9063-core.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/mfd/da9063-core.c b/drivers/mfd/da9063-core.c +index 93db8bb..f38bc98 100644 +--- a/drivers/mfd/da9063-core.c ++++ b/drivers/mfd/da9063-core.c +@@ -118,7 +118,7 @@ int da9063_device_init(struct da9063 *da9063, unsigned int irq) + da9063->irq_base = pdata->irq_base; + } else { + da9063->flags = 0; +- da9063->irq_base = 0; ++ da9063->irq_base = -1; + } + da9063->chip_irq = irq; + +@@ -168,6 +168,8 @@ int da9063_device_init(struct da9063 *da9063, unsigned int irq) + return ret; + } + ++ da9063->irq_base = regmap_irq_chip_get_base(da9063->regmap_irq); ++ + ret = mfd_add_devices(da9063->dev, -1, da9063_devs, + ARRAY_SIZE(da9063_devs), NULL, da9063->irq_base, + NULL); +-- +2.5.0 + diff --git a/recipes-kernel/linux/linux-ge-3.14/0007-mfd-da9063-Add-support-for-OnKey-driver.patch b/recipes-kernel/linux/linux-ge-3.14/0007-mfd-da9063-Add-support-for-OnKey-driver.patch new file mode 100644 index 0000000..b5b9216 --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/0007-mfd-da9063-Add-support-for-OnKey-driver.patch @@ -0,0 +1,114 @@ +From 9d4ceb72253709f7ae6fe02b65eed40053a94902 Mon Sep 17 00:00:00 2001 +From: Steve Twiss +Date: Tue, 19 May 2015 11:32:45 +0100 +Subject: [PATCH 07/10] mfd: da9063: Add support for OnKey driver + +Add MFD support for the DA9063 OnKey driver + +The function da9063_clear_fault_log() is added to mitigate the case of a +hardware power-cut after a long-long OnKey press. Although there is no +software intervention in this case (by definition) such a shutdown would +cause persistent information within the DA9063 FAULT_LOG that would be +available during the next device restart. + +Clearance of this persistent register must be completed after such a +hardware power-cut operation has happened so that the FAULT_LOG does not +continue with previous values. The clearance function has been added here +in the kernel driver because wiping the fault-log cannot be counted on +outside the Linux kernel. + +Signed-off-by: Steve Twiss +[Lee: Removed 'key_power' for Dmitry to take through the Input Tree] +Signed-off-by: Lee Jones +--- + drivers/mfd/da9063-core.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 54 insertions(+) + +diff --git a/drivers/mfd/da9063-core.c b/drivers/mfd/da9063-core.c +index f38bc98..141c2df 100644 +--- a/drivers/mfd/da9063-core.c ++++ b/drivers/mfd/da9063-core.c +@@ -60,6 +60,7 @@ static struct resource da9063_rtc_resources[] = { + + static struct resource da9063_onkey_resources[] = { + { ++ .name = "ONKEY", + .start = DA9063_IRQ_ONKEY, + .end = DA9063_IRQ_ONKEY, + .flags = IORESOURCE_IRQ, +@@ -96,6 +97,7 @@ static const struct mfd_cell da9063_devs[] = { + .name = DA9063_DRVNAME_ONKEY, + .num_resources = ARRAY_SIZE(da9063_onkey_resources), + .resources = da9063_onkey_resources, ++ .of_compatible = "dlg,da9063-onkey", + }, + { + .name = DA9063_DRVNAME_RTC, +@@ -107,12 +109,64 @@ static const struct mfd_cell da9063_devs[] = { + }, + }; + ++static int da9063_clear_fault_log(struct da9063 *da9063) ++{ ++ int ret = 0; ++ int fault_log = 0; ++ ++ ret = regmap_read(da9063->regmap, DA9063_REG_FAULT_LOG, &fault_log); ++ if (ret < 0) { ++ dev_err(da9063->dev, "Cannot read FAULT_LOG.\n"); ++ return -EIO; ++ } ++ ++ if (fault_log) { ++ if (fault_log & DA9063_TWD_ERROR) ++ dev_dbg(da9063->dev, ++ "Fault log entry detected: DA9063_TWD_ERROR\n"); ++ if (fault_log & DA9063_POR) ++ dev_dbg(da9063->dev, ++ "Fault log entry detected: DA9063_POR\n"); ++ if (fault_log & DA9063_VDD_FAULT) ++ dev_dbg(da9063->dev, ++ "Fault log entry detected: DA9063_VDD_FAULT\n"); ++ if (fault_log & DA9063_VDD_START) ++ dev_dbg(da9063->dev, ++ "Fault log entry detected: DA9063_VDD_START\n"); ++ if (fault_log & DA9063_TEMP_CRIT) ++ dev_dbg(da9063->dev, ++ "Fault log entry detected: DA9063_TEMP_CRIT\n"); ++ if (fault_log & DA9063_KEY_RESET) ++ dev_dbg(da9063->dev, ++ "Fault log entry detected: DA9063_KEY_RESET\n"); ++ if (fault_log & DA9063_NSHUTDOWN) ++ dev_dbg(da9063->dev, ++ "Fault log entry detected: DA9063_NSHUTDOWN\n"); ++ if (fault_log & DA9063_WAIT_SHUT) ++ dev_dbg(da9063->dev, ++ "Fault log entry detected: DA9063_WAIT_SHUT\n"); ++ } ++ ++ ret = regmap_write(da9063->regmap, ++ DA9063_REG_FAULT_LOG, ++ fault_log); ++ if (ret < 0) ++ dev_err(da9063->dev, ++ "Cannot reset FAULT_LOG values %d\n", ret); ++ ++ return ret; ++} ++ + int da9063_device_init(struct da9063 *da9063, unsigned int irq) + { + struct da9063_pdata *pdata = da9063->dev->platform_data; + int model, variant_id, variant_code; + int ret; + ++ ret = da9063_clear_fault_log(da9063); ++ if (ret < 0) ++ dev_err(da9063->dev, "Cannot clear fault log\n"); ++ + if (pdata) { + da9063->flags = pdata->flags; + da9063->irq_base = pdata->irq_base; +-- +2.5.0 + diff --git a/recipes-kernel/linux/linux-ge-3.14/0008-ahci_imx-Make-receive-DPLL-mode-configurable.patch b/recipes-kernel/linux/linux-ge-3.14/0008-ahci_imx-Make-receive-DPLL-mode-configurable.patch new file mode 100644 index 0000000..6d39784 --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/0008-ahci_imx-Make-receive-DPLL-mode-configurable.patch @@ -0,0 +1,51 @@ +From 50473c9e2f1db391699e3240a05215ccdb4e81aa Mon Sep 17 00:00:00 2001 +From: Justin Waters +Date: Wed, 2 Mar 2016 11:47:13 -0500 +Subject: [PATCH 08/10] ahci_imx: Make receive DPLL mode configurable + +Signed-off-by: Justin Waters +--- + drivers/ata/ahci_imx.c | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c +index 69422dc..176ca1f 100644 +--- a/drivers/ata/ahci_imx.c ++++ b/drivers/ata/ahci_imx.c +@@ -475,6 +475,13 @@ static const struct reg_value gpr13_rx_eq[] = { + { 4000, IMX6Q_GPR13_SATA_RX_EQ_VAL_4_0_DB }, + }; + ++static const struct reg_value gpr13_rx_dpll[] = { ++ { 0, IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_1F }, ++ { 1, IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_2F }, ++ { 2, IMX6Q_GPR13_SATA_RX_DPLL_MODE_1P_4F }, ++ { 3, IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F }, ++}; ++ + static const struct reg_property gpr13_props[] = { + { + .name = "fsl,transmit-level-mV", +@@ -500,6 +507,11 @@ static const struct reg_property gpr13_props[] = { + .name = "fsl,no-spread-spectrum", + .def_value = IMX6Q_GPR13_SATA_MPLL_SS_EN, + .set_value = 0, ++ }, { ++ .name = "fsl,receive-dpll-mode", ++ .values = gpr13_rx_dpll, ++ .num_values = ARRAY_SIZE(gpr13_rx_dpll), ++ .def_value = IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F, + }, + }; + +@@ -603,7 +615,6 @@ static int imx_ahci_probe(struct platform_device *pdev) + + imxpriv->phy_params = + IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M | +- IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F | + IMX6Q_GPR13_SATA_SPD_MODE_3P0G | + reg_value; + } +-- +2.5.0 + diff --git a/recipes-kernel/linux/linux-ge-3.14/0009-PCI-imx6-Add-DT-bindings-to-configure-PHY-Tx-driver-.patch b/recipes-kernel/linux/linux-ge-3.14/0009-PCI-imx6-Add-DT-bindings-to-configure-PHY-Tx-driver-.patch new file mode 100644 index 0000000..ef12179 --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/0009-PCI-imx6-Add-DT-bindings-to-configure-PHY-Tx-driver-.patch @@ -0,0 +1,112 @@ +From 4227f47441830cf8f639ae7875dc64ced854b068 Mon Sep 17 00:00:00 2001 +From: Justin Waters +Date: Fri, 15 Jan 2016 10:24:35 -0500 +Subject: [PATCH 09/10] PCI: imx6: Add DT bindings to configure PHY Tx driver + settings + +The settings in GPR8 are dependent upon the particular layout of the +hardware platform. As such, they should be configurable via the device +tree. + +Look up PHY Tx driver settings from the device tree. Fall back to the +original hard-coded values if they are not specified in the device tree. + +Signed-off-by: Justin Waters +Signed-off-by: Bjorn Helgaas +Acked-by: Lucas Stach +--- + .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 7 ++++ + drivers/pci/host/pci-imx6.c | 41 +++++++++++++++++++--- + 2 files changed, 43 insertions(+), 5 deletions(-) + +diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +index ad81179..e2f26ff 100644 +--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt ++++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +@@ -19,6 +19,13 @@ Additional required properties for imx6sx-pcie: + - power supplies: + - pcie-phy-supply: regulator used to power the PCIe PHY + ++Optional properties: ++- fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 20 ++- fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 20 ++- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20 ++- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 115 ++- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 115 ++ + Example: + + pcie@0x01000000 { +diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c +index e48091f..cfc51fb 100644 +--- a/drivers/pci/host/pci-imx6.c ++++ b/drivers/pci/host/pci-imx6.c +@@ -58,6 +58,11 @@ struct imx6_pcie { + struct regmap *iomuxc_gpr; + struct regmap *reg_src; + struct regulator *pcie_phy_regulator; ++ u32 tx_deemph_gen1; ++ u32 tx_deemph_gen2_3p5db; ++ u32 tx_deemph_gen2_6db; ++ u32 tx_swing_full; ++ u32 tx_swing_low; + }; + + /* PCIe Root Complex registers (memory-mapped) */ +@@ -522,15 +527,20 @@ static int imx6_pcie_init_phy(struct pcie_port *pp) + IMX6Q_GPR12_LOS_LEVEL, IMX6Q_GPR12_LOS_LEVEL_9); + + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, +- IMX6Q_GPR8_TX_DEEMPH_GEN1, 20 << 0); ++ IMX6Q_GPR8_TX_DEEMPH_GEN1, ++ imx6_pcie->tx_deemph_gen1 << 0); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, +- IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 20 << 6); ++ IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, ++ imx6_pcie->tx_deemph_gen2_3p5db << 6); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, +- IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12); ++ IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, ++ imx6_pcie->tx_deemph_gen2_6db << 12); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, +- IMX6Q_GPR8_TX_SWING_FULL, 115 << 18); ++ IMX6Q_GPR8_TX_SWING_FULL, ++ imx6_pcie->tx_swing_full << 18); + regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, +- IMX6Q_GPR8_TX_SWING_LOW, 115 << 25); ++ IMX6Q_GPR8_TX_SWING_LOW, ++ imx6_pcie->tx_swing_low << 25); + } + + return 0; +@@ -1320,6 +1330,27 @@ static int __init imx6_pcie_probe(struct platform_device *pdev) + return PTR_ERR(imx6_pcie->iomuxc_gpr); + } + ++ /* Grab PCIe PHY Tx Settings */ ++ if (of_property_read_u32(np, "fsl,tx-deemph-gen1", ++ &imx6_pcie->tx_deemph_gen1)) ++ imx6_pcie->tx_deemph_gen1 = 20; ++ ++ if (of_property_read_u32(np, "fsl,tx-deemph-gen2-3p5db", ++ &imx6_pcie->tx_deemph_gen2_3p5db)) ++ imx6_pcie->tx_deemph_gen2_3p5db = 20; ++ ++ if (of_property_read_u32(np, "fsl,tx-deemph-gen2-6db", ++ &imx6_pcie->tx_deemph_gen2_6db)) ++ imx6_pcie->tx_deemph_gen2_6db = 20; ++ ++ if (of_property_read_u32(np, "fsl,tx-swing-full", ++ &imx6_pcie->tx_swing_full)) ++ imx6_pcie->tx_swing_full = 115; ++ ++ if (of_property_read_u32(np, "fsl,tx-swing-low", ++ &imx6_pcie->tx_swing_low)) ++ imx6_pcie->tx_swing_low = 115; ++ + if (IS_ENABLED(CONFIG_EP_MODE_IN_EP_RC_SYS)) { + int i; + void *test_reg1, *test_reg2; +-- +2.5.0 + diff --git a/recipes-kernel/linux/linux-ge-3.14/0010-ARM-dts-imx-Add-support-for-Advantech-GE-ELO.patch b/recipes-kernel/linux/linux-ge-3.14/0010-ARM-dts-imx-Add-support-for-Advantech-GE-ELO.patch new file mode 100644 index 0000000..d0b56ef --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/0010-ARM-dts-imx-Add-support-for-Advantech-GE-ELO.patch @@ -0,0 +1,817 @@ +From 382cafd78e69c6e6a51a8908d3fa787779791e64 Mon Sep 17 00:00:00 2001 +From: Justin Waters +Date: Fri, 12 Dec 2014 17:12:24 -0500 +Subject: [PATCH 10/10] ARM: dts: imx: Add support for Advantech/GE ELO + +Add support for the Advantech/GE ELO Board. + +Signed-off-by: Justin Waters +--- + arch/arm/boot/dts/imx6q-elo.dts | 795 ++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 795 insertions(+) + create mode 100644 arch/arm/boot/dts/imx6q-elo.dts + +diff --git a/arch/arm/boot/dts/imx6q-elo.dts b/arch/arm/boot/dts/imx6q-elo.dts +new file mode 100644 +index 0000000..7442e2c +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-elo.dts +@@ -0,0 +1,795 @@ ++/* ++ * Copyright 2016 Timesys Corporation ++ * Copyright 2016 General Electric Company ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++ ++#include "imx6q.dtsi" ++ ++/ { ++ model = "General Electric ELO"; ++ compatible = "fsl,imx6q-elo", "fsl,imx6q"; ++ ++ aliases { ++ mxcfb0 = &mxcfb1; ++ mxcfb1 = &mxcfb2; ++ mmc0 = &usdhc2; ++ mmc1 = &usdhc3; ++ mmc2 = &usdhc4; ++ }; ++ ++ memory { ++ reg = <0x10000000 0x40000000>; ++ }; ++ ++ clocks { ++ clk24m: clk24m { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <24000000>; ++ }; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ ++ reg_usb_otg_vbus: usb_otg_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_otg_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ reg_usb_h1_vbus: usb_h1_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_h1_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++ ++ reg_1p8v: 1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1P8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: 3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_lvds: regulator-lvds { ++ compatible = "regulator-fixed"; ++ regulator-name = "lvds_ppen"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ }; ++ ++ sound { ++ compatible = "fsl,imx6q-ba16-sgtl5000", ++ "fsl,imx-audio-sgtl5000"; ++ model = "imx6q-ba16-sgtl5000"; ++ cpu-dai = <&ssi1>; ++ audio-codec = <&codec>; ++ audio-routing = ++ "MIC_IN", "Mic Jack", ++ "Mic Jack", "Mic Bias", ++ "Headphone Jack", "HP_OUT"; ++ mux-int-port = <1>; ++ mux-ext-port = <4>; ++ }; ++ ++ sound-hdmi { ++ compatible = "fsl,imx6q-audio-hdmi", ++ "fsl,imx-audio-hdmi"; model = "imx-audio-hdmi"; ++ hdmi-controller = <&hdmi_audio>; ++ }; ++ ++ mxcfb1: fb@0 { ++ compatible = "fsl,mxc_sdc_fb"; ++ disp_dev = "ldb"; ++ interface_pix_fmt = "RGB24"; ++ default_bpp = <32>; ++ int_clk = <0>; ++ late_init = <0>; ++ status = "okay"; ++ }; ++ ++ mxcfb2: fb@1 { ++ compatible = "fsl,mxc_sdc_fb"; ++ disp_dev = "hdmi"; ++ interface_pix_fmt = "RGB24"; ++ mode_str ="1920x1080M@60"; ++ default_bpp = <24>; ++ int_clk = <0>; ++ late_init = <0>; ++ status = "okay"; ++ }; ++ ++ backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm1 0 5000000>; ++ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 ++ 10 11 12 13 14 15 16 17 18 19 ++ 20 21 22 23 24 25 26 27 28 29 ++ 30 31 32 33 34 35 36 37 38 39 ++ 40 41 42 43 44 45 46 47 48 49 ++ 50 51 52 53 54 55 56 57 58 59 ++ 60 61 62 63 64 65 66 67 68 69 ++ 70 71 72 73 74 75 76 77 78 79 ++ 80 81 82 83 84 85 86 87 88 89 ++ 90 91 92 93 94 95 96 97 98 99 ++ 100 101 102 103 104 105 106 107 108 109 ++ 110 111 112 113 114 115 116 117 118 119 ++ 120 121 122 123 124 125 126 127 128 129 ++ 130 131 132 133 134 135 136 137 138 139 ++ 140 141 142 143 144 145 146 147 148 149 ++ 150 151 152 153 154 155 156 157 158 159 ++ 160 161 162 163 164 165 166 167 168 169 ++ 170 171 172 173 174 175 176 177 178 179 ++ 180 181 182 183 184 185 186 187 188 189 ++ 190 191 192 193 194 195 196 197 198 199 ++ 200 201 202 203 204 205 206 207 208 209 ++ 210 211 212 213 214 215 216 217 218 219 ++ 220 221 222 223 224 225 226 227 228 229 ++ 230 231 232 233 234 235 236 237 238 239 ++ 240 241 242 243 244 245 246 247 248 249 ++ 250 251 252 253 254 255>; ++ default-brightness-level = <255>; ++ power-supply = <®_lvds>; ++ enable-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ v4l2_out { ++ compatible = "fsl,mxc_v4l2_output"; ++ status = "okay"; ++ }; ++}; ++ ++&audmux { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_audmux>; ++ status = "okay"; ++}; ++ ++&clks { ++ fsl,ldb-di0-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; ++ fsl,ldb-di1-parent = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; ++}; ++ ++&ecspi1 { ++ fsl,spi-num-chipselects = <1>; ++ cs-gpios = <&gpio2 30 0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ecspi1>; ++ status = "okay"; ++ ++ flash: n25q032@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "st,n25q032"; ++ spi-max-frequency = <20000000>; ++ reg = <0>; ++ partition@0 { ++ label = "U-Boot"; ++ reg = <0x0 0xC0000>; ++ }; ++ partition@C0000 { ++ label = "env"; ++ reg = <0xC0000 0x10000>; ++ }; ++ partition@D0000 { ++ label = "spare"; ++ reg = <0xD0000 0x130000>; ++ }; ++ }; ++}; ++ ++&ecspi5 { ++ fsl,spi-num-chipselects = <1>; ++ cs-gpios = <&gpio1 17 0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ecspi5>; ++ status = "okay"; ++ ++ m25_eeprom: m25p80@0 { ++ compatible = "atmel,at25"; ++ spi-max-frequency = <20000000>; ++ size = <0x8000>; ++ pagesize = <64>; ++ reg = <0>; ++ address-width = <16>; ++ }; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet>; ++ phy-mode = "rgmii"; ++ status = "okay"; ++}; ++ ++&cpu0 { ++ arm-supply = <®_arm>; ++ soc-supply = <®_soc>; ++ pu-supply = <®_pu>; ++}; ++ ++&dcic1 { ++ dcic_id = <0>; ++ dcic_mux = "dcic-hdmi"; ++ status = "okay"; ++}; ++ ++&dcic2 { ++ dcic_id = <1>; ++ dcic_mux = "dcic-lvds1"; ++ status = "okay"; ++}; ++ ++ ++&gpc { ++ fsl,cpu_pupscr_sw2iso = <0xf>; ++ fsl,cpu_pupscr_sw = <0xf>; ++ fsl,cpu_pdnscr_iso2sw = <0x1>; ++ fsl,cpu_pdnscr_iso = <0x1>; ++ fsl,ldo-bypass = <0>; ++ fsl,wdog-reset = <1>; /* watchdog select of reset source */ ++ pu-supply = <®_pu>; ++}; ++ ++&hdmi_audio { ++ status = "okay"; ++}; ++ ++&hdmi_cec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hdmi_cec>; ++ status = "okay"; ++}; ++ ++&hdmi_core { ++ ipu_id = <1>; ++ disp_id = <0>; ++ status = "okay"; ++}; ++ ++&hdmi_video { ++ fsl,phy_reg_vlev = <0x01ad>; ++ fsl,phy_reg_cksymtx = <0x800d>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1>; ++ status = "okay"; ++ ++ codec: sgtl5000@0a { ++ compatible = "fsl,sgtl5000"; ++ reg = <0x0a>; ++ clocks = <&clks 201>; ++ VDDA-supply = <®_1p8v>; ++ VDDIO-supply = <®_3p3v>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2>; ++ status = "okay"; ++ ++ hdmi: edid@50 { ++ compatible = "fsl,imx6-hdmi-i2c"; ++ reg = <0x50>; ++ }; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3>; ++ status = "okay"; ++ ++ pmic@58 { ++ compatible = "dialog,da9063"; ++ reg = <0x58>; ++ interrupt-parent = <&gpio7>; ++ interrupts = <13 0x8>; /* active-low GPIO7_13 */ ++ ++ regulators { ++ bcore1 { ++ regulator-min-microvolt = <1420000>; ++ regulator-max-microvolt = <1420000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ bcore2 { ++ regulator-min-microvolt = <1420000>; ++ regulator-max-microvolt = <1420000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ bpro { ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ bmem { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ bio: bio { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ bperi: bperi { ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ ldo1 { ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1860000>; ++ }; ++ ++ ldo2 { ++ regulator-min-microvolt = <600000>; ++ regulator-max-microvolt = <1860000>; ++ }; ++ ++ ldo3 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <3440000>; ++ }; ++ ++ ldo4 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <3440000>; ++ }; ++ ++ ldo5 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <3600000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ ldo6 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <3600000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ ldo7 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <3600000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ ldo8 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <3600000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ ldo9 { ++ regulator-min-microvolt = <950000>; ++ regulator-max-microvolt = <3600000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ ldo10 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <3600000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ ldo11 { ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <3600000>; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ }; ++ }; ++ ++ rtc@32 { ++ compatible = "epson,rx8010"; ++ reg = <0x32>; ++ interrupt-parent = <&gpio4>; ++ interrupts = <10>; ++ rx8010-irq_1 = <&gpio4 10 0>; ++ }; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ hog { ++ pinctrl_hog: hoggrp-1 { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* uSDHC2 CD */ ++ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 /* uSDHC4 CD */ ++ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 /* uSDHC4 SDIO PWR */ ++ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 /* uSDHC4 SDIO WP */ ++ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 /* uSDHC4 SDIO LED */ ++ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x80000000 /* SPI1 CS */ ++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* FEC Reset */ ++ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 /* GPIO0 */ ++ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 /* GPIO1 */ ++ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 /* GPIO2 */ ++ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 /* GPIO3 */ ++ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 /* GPIO4 */ ++ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 /* GPIO5 */ ++ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000 /* GPIO6 */ ++ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000 /* GPIO7 */ ++ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 /* CAM_PWDN */ ++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAM_RST */ ++ MX6QDL_PAD_GPIO_9__WDOG1_B 0x80000000 /* Watchdog out */ ++ MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x80000000 /* HUB_RESET */ ++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x80000000 /* PMIC Interrupt */ ++ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* AR8033 Interrupt */ ++ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* BLEN_OUT */ ++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* LVDS_PPEN_OUT */ ++ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* RTC_INT */ ++ >; ++ }; ++ }; ++ ++ usdhc3 { ++ pinctrl_usdhc3_reset: usdhc3grp-reset { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_RST__SD3_RESET 0x170F9 ++ >; ++ }; ++ }; ++ ++ audmux { ++ pinctrl_audmux: audmuxgrp { ++ fsl,pins = < ++ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0 ++ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0 ++ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0 ++ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0 ++ >; ++ }; ++ }; ++ ++ ecspi1 { ++ pinctrl_ecspi1: ecspi1grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 ++ MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 ++ MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 ++ >; ++ }; ++ }; ++ ++ ecspi5 { ++ pinctrl_ecspi5: ecspi5grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x1b0b0 ++ MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x1b0b0 ++ MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x1b0b0 ++ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0 ++ >; ++ }; ++ }; ++ ++ hdmi_cec { ++ pinctrl_hdmi_cec: hdmicecgrp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 ++ >; ++ }; ++ }; ++ ++ usbotg { ++ pinctrl_usbotg: usbotggrp { ++ fsl,pins = < ++ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 ++ >; ++ }; ++ }; ++ ++ usdhc2 { ++ pinctrl_usdhc2: usdhc2grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 ++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 ++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 ++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 ++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 ++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 ++ >; ++ }; ++ }; ++ ++ usdhc3 { ++ pinctrl_usdhc3: usdhc3grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 ++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 ++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 ++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 ++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 ++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 ++ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 ++ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 ++ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 ++ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 ++ >; ++ }; ++ }; ++ ++ usdhc4 { ++ pinctrl_usdhc4: usdhc4grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 ++ MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 ++ MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 ++ MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 ++ MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 ++ MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 ++ MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 ++ MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 ++ MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 ++ MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 ++ >; ++ }; ++ }; ++ ++ i2c1 { ++ pinctrl_i2c1: i2c1grp { ++ fsl,pins = < ++ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 ++ MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 ++ >; ++ }; ++ }; ++ ++ i2c2 { ++ pinctrl_i2c2: i2c2grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 ++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 ++ >; ++ }; ++ }; ++ ++ i2c3 { ++ pinctrl_i2c3: i2c3grp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 ++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 ++ >; ++ }; ++ }; ++ ++ pwm1 { ++ pinctrl_pwm1: pwm1grp { ++ fsl,pins = < ++ MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 ++ >; ++ }; ++ }; ++ ++ pwm2 { ++ pinctrl_pwm2: pwm2grp { ++ fsl,pins = < ++ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 ++ >; ++ }; ++ }; ++ ++ enet { ++ pinctrl_enet: enetgrp { ++ fsl,pins = < ++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 ++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 ++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 ++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 ++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 ++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 ++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 ++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 ++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 ++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 ++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 ++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 ++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 ++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 ++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 ++ >; ++ }; ++ }; ++ ++ uart3 { ++ pinctrl_uart3: uart3grp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 ++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 ++ MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 ++ >; ++ }; ++ }; ++ ++ uart4 { ++ pinctrl_uart4: uart4grp { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 ++ >; ++ }; ++ }; ++}; ++ ++&ldb { ++ split-mode; ++ status = "okay"; ++ ++ lvds-channel@0 { ++ fsl,data-mapping = "spwg"; ++ fsl,data-width = <24>; ++ crtc = "ipu1-di0"; ++ status = "okay"; ++ ++ display-timings { ++ native-mode = <&timing0>; ++ timing0: SHARP-LQ156M1LG21 { ++ clock-frequency = <65000000>; ++ hactive = <1920>; ++ vactive = <1080>; ++ hback-porch = <100>; ++ hfront-porch = <40>; ++ vback-porch = <30>; ++ vfront-porch = <3>; ++ hsync-len = <10>; ++ vsync-len = <2>; ++ }; ++ }; ++ }; ++ ++ lvds-channel@1 { ++ status = "disabled"; ++ }; ++}; ++ ++&pcie { ++ reset-gpio = <&gpio7 12 0>; ++ fsl,tx-deemph-gen1 = <0>; ++ fsl,tx-deemph-gen2-3p5db = <0>; ++ fsl,tx-deemph-gen2-6db = <20>; ++ fsl,tx-swing-full = <103>; ++ fsl,tx-swing-low = <103>; ++ status = "okay"; ++}; ++ ++ ++&pwm1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm1>; ++ status = "okay"; ++}; ++ ++&pwm2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm2>; ++ status = "okay"; ++}; ++ ++&ssi1 { ++ fsl,mode = "i2s-master"; ++ status = "okay"; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart3>; ++ fsl,uart-has-rtscts; ++ status = "okay"; ++}; ++ ++&uart4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart4>; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ vbus-supply = <®_usb_h1_vbus>; ++ reset-gpios = <&gpio7 11 0>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_usb_otg_vbus>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbotg>; ++ disable-over-current; ++ status = "okay"; ++}; ++ ++&usdhc2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc2>; ++ cd-gpios = <&gpio1 4 0>; ++ no-1-8-v; ++ keep-power-in-suspend; ++ enable-sdio-wakeup; ++ status = "okay"; ++}; ++ ++&usdhc3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; ++ bus-width = <8>; ++ vmmc-supply = <&bperi>; ++ no-1-8-v; ++ non-removable; ++ keep-power-in-suspend; ++ status = "okay"; ++}; ++ ++&usdhc4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc4>; ++ bus-width = <8>; ++ cd-gpios = <&gpio6 11 0>; ++ no-1-8-v; ++ keep-power-in-suspend; ++ enable-sdio-wakeup; ++ status = "okay"; ++}; ++ ++&vpu { ++ pu-supply = <®_pu>; ++}; ++ ++&sata { ++ fsl,no-spread-spectrum; ++ fsl,transmit-atten-16ths = <12>; ++ fsl,transmit-boost-mdB = <3330>; ++ fsl,transmit-level-mV = <1133>; ++ fsl,receive-dpll-mode = <1>; ++ status = "okay"; ++}; +-- +2.5.0 + diff --git a/recipes-kernel/linux/linux-ge-3.14/defconfig b/recipes-kernel/linux/linux-ge-3.14/defconfig new file mode 100644 index 0000000..86c6caf --- /dev/null +++ b/recipes-kernel/linux/linux-ge-3.14/defconfig @@ -0,0 +1,453 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_MXC=y +CONFIG_MACH_IMX51_DT=y +CONFIG_MACH_EUKREA_CPUIMX51SD=y +CONFIG_SOC_IMX50=y +CONFIG_SOC_IMX53=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_SOC_IMX6SX=y +CONFIG_SOC_IMX6UL=y +CONFIG_SOC_IMX7D=y +CONFIG_SOC_VF610=y +# CONFIG_SWP_EMULATE is not set +CONFIG_PCI=y +CONFIG_PCI_IMX6=y +CONFIG_SMP=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_CMA=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_KEXEC=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_ARM_IMX7D_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_VLAN_8021Q=y +CONFIG_LLC2=y +CONFIG_CAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_CAN_M_CAN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_HCIBTUSB=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIBCM203X=y +CONFIG_BT_ATH3K=y +CONFIG_CFG80211=y +CONFIG_MAC80211=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=320 +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_SPI_NOR=y +CONFIG_SPI_FSL_QUADSPI=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_SENSORS_FXOS8700=y +CONFIG_SENSORS_FXAS2100X=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_CS89x0=y +CONFIG_CS89x0_PLATFORM=y +# CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_IGB=y +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMC91X=y +CONFIG_SMC911X=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_MICREL_PHY=y +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_BCMDHD=m +CONFIG_BCMDHD_SDIO=y +CONFIG_BCMDHD_FW_PATH="/lib/firmware/bcm/fw_bcmdhd.bin" +CONFIG_BCMDHD_NVRAM_PATH="/lib/firmware/bcm/bcmdhd.cal" +# CONFIG_RTL_CARDS is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +CONFIG_MOUSE_PS2=m +CONFIG_MOUSE_PS2_ELANTECH=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_ELAN=y +CONFIG_TOUCHSCREEN_MAX11801=y +CONFIG_TOUCHSCREEN_IMX6UL_TSC=y +CONFIG_TOUCHSCREEN_MC13783=y +CONFIG_TOUCHSCREEN_TSC2007=y +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_MMA8450=y +CONFIG_INPUT_ISL29023=y +CONFIG_INPUT_MPL3115=y +CONFIG_SENSOR_FXLS8471=y +CONFIG_SERIO_SERPORT=m +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +CONFIG_FSL_OTP=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_MAX732X=y +CONFIG_GPIO_74X164=y +CONFIG_POWER_SUPPLY=y +CONFIG_SABRESD_MAX8903=y +CONFIG_SENSORS_MAX17135=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_DA9052_I2C=y +CONFIG_MFD_DA9063=y +CONFIG_MFD_MC13XXX_SPI=y +CONFIG_MFD_MC13XXX_I2C=y +CONFIG_MFD_MAX17135=y +CONFIG_MFD_SI476X_CORE=y +CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_DA9052=y +CONFIG_REGULATOR_DA9063=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX17135=y +CONFIG_REGULATOR_MC13783=y +CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +CONFIG_MEDIA_RC_SUPPORT=y +CONFIG_RC_DEVICES=y +CONFIG_IR_GPIO_CIR=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_VADC=m +CONFIG_MXC_MIPI_CSI=m +CONFIG_MXC_CAMERA_OV5647_MIPI=m +CONFIG_SOC_CAMERA=y +CONFIG_VIDEO_MX3=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CODA=y +CONFIG_RADIO_SI476X=y +CONFIG_SOC_CAMERA_OV2640=y +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_MIPI_DSI_SAMSUNG=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXC_EINK_PANEL=y +CONFIG_FB_MXC_EINK_V2_PANEL=y +CONFIG_FB_MXS_SII902X=y +CONFIG_FB_MXC_DCIC=m +CONFIG_HANNSTAR_CABC=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_EUKREA_TLV320=y +CONFIG_SND_SOC_IMX_CS42888=y +CONFIG_SND_SOC_IMX_SII902X=y +CONFIG_SND_SOC_IMX_WM8958=y +CONFIG_SND_SOC_IMX_WM8960=y +CONFIG_SND_SOC_IMX_WM8962=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_MQS=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_MC13783=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_SND_SOC_IMX_SI476X=y +CONFIG_USB=y +CONFIG_USB_OTG_WHITELIST=y +CONFIG_USB_OTG_FSM=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_HCD_TEST_MODE=y +CONFIG_USB_ACM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_EHSET_TEST_FIXTURE=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_IPU_V3_PRE=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_MXC_SIM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DA9063=y +CONFIG_RTC_DRV_MC13XXX=y +CONFIG_RTC_DRV_MXC=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_V3=y +CONFIG_IMX_SDMA=y +CONFIG_MXS_DMA=y +CONFIG_STAGING=y +CONFIG_STAGING_MEDIA=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IIO=y +CONFIG_VF610_ADC=y +CONFIG_AD2802A=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_DEBUG_FS=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SINK_TPIU=y +CONFIG_CORESIGHT_SINK_ETBV10=y +CONFIG_CORESIGHT_SOURCE_ETM3X=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_TWOFISH=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/recipes-kernel/linux/linux-ge_3.14.bb b/recipes-kernel/linux/linux-ge_3.14.bb new file mode 100644 index 0000000..6ccf0ab --- /dev/null +++ b/recipes-kernel/linux/linux-ge_3.14.bb @@ -0,0 +1,25 @@ +# Copyright (C) 2016 Timesys Corporation +# Copyright (C) 2016 General Electric Company +# Released under the MIT license (see COPYING.MIT for the terms) + +include recipes-kernel/linux/linux-imx.inc +include recipes-kernel/linux/linux-dtb.inc + +DEPENDS += "lzop-native bc-native" + +SRCREV = "5668cd93fe86889e121142440b42d4615afae984" +LOCALVERSION = "-1.1.x-fslc-imx-elo" +SRC_URI = "git://github.com/Freescale/linux-fslc.git;branch=3.14-1.1.x-imx \ + file://0001-rtc-rx8010-Add-driver-to-kernel.patch \ + file://0002-mfd-da9063-Add-support-for-production-silicon-varian.patch \ + file://0003-mfd-da9063-Upgrade-of-register-definitions-to-suppor.patch \ + file://0004-rtc-da9063-RTC-driver.patch \ + file://0005-mfd-da9063-Add-support-for-AD-silicon-variant.patch \ + file://0006-mfd-da9063-Get-irq-base-dynamically-before-registeri.patch \ + file://0007-mfd-da9063-Add-support-for-OnKey-driver.patch \ + file://0008-ahci_imx-Make-receive-DPLL-mode-configurable.patch \ + file://0009-PCI-imx6-Add-DT-bindings-to-configure-PHY-Tx-driver-.patch \ + file://0010-ARM-dts-imx-Add-support-for-Advantech-GE-ELO.patch \ + file://defconfig" + +COMPATIBLE_MACHINE = "(imx6q-elo)"