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bd0f35ad04
Add support for Solid-Runs LX2160A based COM Express Type 7 Module and machines built upon that module (see https://www.solid-run.com/nxp-lx2160a-family/). Signed-off-by: Jens Rehsack <sno@netbsd.org>
226 lines
4.5 KiB
Diff
226 lines
4.5 KiB
Diff
From 35dc5b03bb8f7b93fb474c39d7689d39062ff81a Mon Sep 17 00:00:00 2001
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From: Rabeeh Khoury <rabeeh@solid-run.com>
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Date: Sun, 28 Jul 2019 14:21:06 +0300
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Subject: [PATCH 2/3] arm64: dts: lx2160a: add lx2160acex7 device tree
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The device tree enables the following features -
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1. dpmac17 RGMII MAC connected to Atheros AR8035 phy
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2. 2x MDIO busses
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3. 2x USB 3.0 controllers
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4. 4x SATA ports
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5. MT35X 512Mb SPI flash
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6. Temperature sensor on i2c0 channel 3
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7. AMC6821 temperature and PWM fan controller
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The module supports AMC6821 and EMC2301 PWM controllers where either can
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be assembled, but not both together since the PWM and TACH signals are
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shared between them.
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Upstream-Status: Inappropriate [Solid-Run BSP]
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Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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---
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.../boot/dts/freescale/fsl-lx2160a-cex7.dts | 190 ++++++++++++++++++
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1 file changed, 190 insertions(+)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
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diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
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new file mode 100644
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index 000000000000..872fcf9e724d
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
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@@ -0,0 +1,190 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+//
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+// Device Tree file for LX2160A-CEx7
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+//
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+// Copyright 2019 SolidRun ltd.
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+
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+/dts-v1/;
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+
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+#include "fsl-lx2160a.dtsi"
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+
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+/ {
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+ model = "SolidRun LX2160A COM express type 7 module";
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+ compatible = "fsl,lx2160a-cex7", "fsl,lx2160a";
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+
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+ aliases {
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+ crypto = &crypto;
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+ serial0 = &uart0;
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+ serial1 = &uart1;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ sb_3v3: regulator-sb3v3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "RT7290";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+};
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+
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+&crypto {
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+ status = "okay";
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+};
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+
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+&esdhc0 {
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+ sd-uhs-sdr104;
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+ sd-uhs-sdr50;
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+ sd-uhs-sdr25;
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+ sd-uhs-sdr12;
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+ status = "okay";
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+};
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+
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+&esdhc1 {
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+ mmc-hs200-1_8v;
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+ mmc-hs400-1_8v;
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+ bus-width = <8>;
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+ status = "okay";
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+};
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+
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+
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+/*
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+i2c busses are -
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+/dev/i2c0 - CTRL #0 - connected to PCA9547 I2C switch
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+/dev/i2c1 - CTRL #2 - COM module to carrier (general I2C_CK/I2C_DAT)
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+/dev/i2c2 - CTRL #4 - Connected to RTC PCF2129AT (0x51), EEPROM (0x54,0x55,0x56,0x57)
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+
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+I2C switch -
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+/dev/i2c3 - CH0 - SO-DIMMs SPD (0x51, 0x53), 2Kb EEPROM (0x57), bootable 512Kb eeprom (0x50)
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+/dev/i2c4 - CH1 - 100MHz clk gen (address 0x6a)
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+/dev/i2c5 - CH2 - LTC3882 DC-DC controller on 0x63
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+/dev/i2c6 - CH3 - SA56004ED (0x4c), SA56004FD (0x4d), COM module SMB_CK,SMB_DAT and COM module 10G_LED_SDA,10G_LED_SCL
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+/dev/i2c7 - CH4 - SFP #0 I2C
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+/dev/i2c8 - CH5 - SFP #1 I2C
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+/dev/i2c9 - CH6 - SFP #2 I2C
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+/dev/i2c10 - CH7 - SFP #3 I2C
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+
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+
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+*/
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+
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+
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+
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+&i2c0 {
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+ status = "okay";
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+
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+ i2c-mux@77 {
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+ compatible = "nxp,pca9547";
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+ reg = <0x77>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ i2c@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x1>;
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+ fan-temperature-ctrlr@18 {
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+ compatible = "ti,amc6821";
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+ reg = <0x18>;
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+ cooling-min-state = <0>;
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+ cooling-max-state = <9>;
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+ #cooling-cells = <2>;
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+ };
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+ };
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+ i2c@3 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x3>;
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+
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+ temperature-sensor@48 {
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+ compatible = "nxp,sa56004";
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+ reg = <0x48>;
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+ vcc-supply = <&sb_3v3>;
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+ };
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+ };
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+ };
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+};
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+
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+&i2c2 {
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+ status = "okay";
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+};
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+
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+&i2c4 {
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+ status = "okay";
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+
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+ rtc@51 {
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+ compatible = "nxp,pcf2129";
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+ reg = <0x51>;
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+ // IRQ10_B
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+ interrupts = <0 150 0x4>;
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+ };
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+};
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+
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+&fspi {
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+ status = "okay";
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+ flash0: mt35xu512aba@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "micron,m25p80";
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+ m25p,fast-read;
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+ spi-max-frequency = <50000000>;
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+ reg = <0>;
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+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
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+ spi-rx-bus-width = <8>;
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+ spi-tx-bus-width = <1>;
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+ };
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ status = "okay";
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+};
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+
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+&usb0 {
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+ status = "okay";
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+};
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+
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+&usb1 {
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+ status = "okay";
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+};
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+
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+&emdio1 {
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+ status = "okay";
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+ rgmii_phy1: ethernet-phy@1 {
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+ /* AR8035 PHY - "compatible" property not strictly needed */
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+ compatible = "ethernet-phy-id004d.d072";
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+ reg = <0x1>;
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+ /* Poll mode - no "interrupts" property defined */
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+ };
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+};
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+
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+&emdio2 {
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+ status = "okay";
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+};
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+
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+&dpmac17 {
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+ phy-handle = <&rgmii_phy1>;
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+ phy-connection-type = "rgmii-id";
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+};
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+
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+&sata0 {
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+ status = "okay";
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+};
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+
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+&sata1 {
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+ status = "okay";
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+};
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+
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+&sata2 {
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+ status = "okay";
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+};
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+
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+&sata3 {
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+ status = "okay";
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+};
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--
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2.17.1
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