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faa6023723
The support for the ConnectCore 6UL SOM and SBC Express is available in v4.19 so it is added as patches here. The GPMI BCH layout change is needed to match the kernel with the NXP IMX vendor based U-Boot used in the ConnectCore 6UL SOM. Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
40 lines
1.2 KiB
Diff
40 lines
1.2 KiB
Diff
From 6e7242f21f0d9461e1ad3b13a4118c44e17cfa38 Mon Sep 17 00:00:00 2001
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From: Anson Huang <Anson.Huang@nxp.com>
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Date: Fri, 14 Sep 2018 10:59:21 +0800
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Subject: [PATCH 3/5] ARM: dts: imx6ul: use nvmem-cells for cpu speed grading
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On i.MX6UL, accessing OCOTP directly is wrong because the ocotp clock
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needs to be enabled first, so use the nvmem-cells binding instead.
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Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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(cherry picked from commit 92f0eb08c66a73594cf200e65689e767f7f0da5e)
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---
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arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
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1 file changed, 6 insertions(+)
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diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
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index 47a3453a4211..9670f15bcb31 100644
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--- a/arch/arm/boot/dts/imx6ul.dtsi
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+++ b/arch/arm/boot/dts/imx6ul.dtsi
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@@ -88,6 +88,8 @@
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"pll1_sys";
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arm-supply = <®_arm>;
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soc-supply = <®_soc>;
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+ nvmem-cells = <&cpu_speed_grade>;
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+ nvmem-cell-names = "speed_grade";
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};
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};
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@@ -926,6 +928,10 @@
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tempmon_temp_grade: temp-grade@20 {
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reg = <0x20 4>;
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};
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+
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+ cpu_speed_grade: speed-grade@10 {
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+ reg = <0x10 4>;
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+ };
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};
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lcdif: lcdif@21c8000 {
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