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faa6023723
The support for the ConnectCore 6UL SOM and SBC Express is available in v4.19 so it is added as patches here. The GPMI BCH layout change is needed to match the kernel with the NXP IMX vendor based U-Boot used in the ConnectCore 6UL SOM. Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
245 lines
5.9 KiB
Diff
245 lines
5.9 KiB
Diff
From 9ca4211642dc7d6521594b58600ecab8088039e2 Mon Sep 17 00:00:00 2001
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From: Alex Gonzalez <alex.gonzalez@digi.com>
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Date: Thu, 12 Jul 2018 10:20:36 +0200
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Subject: [PATCH 5/5] ARM: dts: imx6ul: Add DTS for ConnectCore 6UL SBC Express
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The ConnectCore 6UL Single Board Computer (SBC) Express contains the
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ConnectCore 6UL System-On-Module.
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Its hardware specifications are:
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* 256MB DDR3 memory
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* 256MB NAND flash
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* Single Ethernet
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* USB Host and USB-OTG
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* MicroSD external storage
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* Groove connectors and Raspberry Pi Hat compatible expansion header
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Signed-off-by: Alex Gonzalez <alex.gonzalez@digi.com>
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Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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(cherry picked from commit 8c7725829989d2711875f60356d22bc5af981ac0)
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---
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arch/arm/boot/dts/Makefile | 1 +
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arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts | 200 ++++++++++++++++++++++++
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2 files changed, 201 insertions(+)
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create mode 100644 arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts
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diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
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index 37a3de760d40..6135d3dc381c 100644
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--- a/arch/arm/boot/dts/Makefile
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+++ b/arch/arm/boot/dts/Makefile
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@@ -533,6 +533,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
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imx6sx-udoo-neo-full.dtb
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dtb-$(CONFIG_SOC_IMX6UL) += \
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imx6ul-14x14-evk.dtb \
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+ imx6ul-ccimx6ulsbcexpress.dtb \
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imx6ul-geam.dtb \
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imx6ul-isiot-emmc.dtb \
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imx6ul-isiot-nand.dtb \
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diff --git a/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts
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new file mode 100644
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index 000000000000..3792679c0c90
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--- /dev/null
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+++ b/arch/arm/boot/dts/imx6ul-ccimx6ulsbcexpress.dts
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@@ -0,0 +1,200 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Digi International's ConnectCore6UL SBC Express board device tree source
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+ *
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+ * Copyright 2018 Digi International, Inc.
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+ *
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+ */
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+
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+/dts-v1/;
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+#include <dt-bindings/input/input.h>
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+#include <dt-bindings/interrupt-controller/irq.h>
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+#include "imx6ul.dtsi"
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+#include "imx6ul-ccimx6ulsom.dtsi"
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+
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+/ {
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+ model = "Digi International ConnectCore 6UL SBC Express.";
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+ compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom",
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+ "fsl,imx6ul";
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+};
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+
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+&adc1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_adc1>;
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+ status = "okay";
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+};
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+
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+&can1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_flexcan1>;
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+ xceiver-supply = <&ext_3v3>;
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+ status = "okay";
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+};
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+
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+&ecspi3 {
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+ cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_ecspi3_master>;
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+ status = "okay";
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+};
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+
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+&fec1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_enet1>;
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+ phy-mode = "rmii";
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+ phy-handle = <ðphy0>;
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+ status = "okay";
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ethphy0: ethernet-phy@0 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ smsc,disable-energy-detect;
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+ reg = <0>;
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+ };
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+ };
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+};
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+
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+&i2c2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_i2c2>;
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+ status = "okay";
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+};
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+
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+&pwm1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_pwm1>;
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+ status = "okay";
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+};
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+
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+&uart4 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_uart4>;
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+ status = "okay";
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+};
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+
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+&uart5 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_uart5>;
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+ status = "okay";
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+};
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+
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+&usbotg1 {
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+ dr_mode = "host";
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+ disable-over-current;
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+ status = "okay";
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+};
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+
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+&usbotg2 {
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+ dr_mode = "host";
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+ disable-over-current;
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+ status = "okay";
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+};
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+
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+&usdhc2 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_usdhc2>;
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+ broken-cd; /* no carrier detect line (use polling) */
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+ no-1-8-v;
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+ status = "okay";
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+};
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+
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+&iomuxc {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_hog>;
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+
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+ pinctrl_adc1: adc1grp {
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+ fsl,pins = <
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+ /* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */
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+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
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+ >;
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+ };
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+
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+ pinctrl_ecspi3_master: ecspi3grp1 {
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+ fsl,pins = <
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+ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
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+ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
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+ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
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+ MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 /* Chip Select */
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+ >;
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+ };
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+
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+ pinctrl_ecspi3_slave: ecspi3grp2 {
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+ fsl,pins = <
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+ MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0
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+ MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0
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+ MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0
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+ MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x10b0 /* Chip Select */
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+ >;
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+ };
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+
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+ pinctrl_enet1: enet1grp {
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+ fsl,pins = <
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+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40017051
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+ >;
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+ };
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+
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+ pinctrl_flexcan1: flexcan1grp{
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+ fsl,pins = <
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+ MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020
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+ MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020
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+ >;
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+ };
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+
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+ pinctrl_i2c2: i2c2grp {
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+ fsl,pins = <
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+ MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
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+ MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
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+ >;
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+ };
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+
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+ pinctrl_pwm1: pwm1grp {
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+ fsl,pins = <
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+ MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x10b0
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+ >;
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+ };
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+
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+ pinctrl_uart4: uart4grp {
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+ fsl,pins = <
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+ MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x1b0b1
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+ MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x1b0b1
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+ >;
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+ };
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+
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+ pinctrl_uart5: uart5grp {
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+ fsl,pins = <
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+ MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x1b0b1
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+ MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x1b0b1
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+ >;
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+ };
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+
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+ pinctrl_usdhc2: usdhc2grp {
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+ fsl,pins = <
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+ MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
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+ MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10071
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+ MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
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+ MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
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+ MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
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+ MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
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+ >;
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+ };
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+
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+ /* General purpose pinctrl */
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+ pinctrl_hog: hoggrp {
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+ fsl,pins = <
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+ /* GPIOs BANK 3 */
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+ MX6UL_PAD_LCD_RESET__GPIO3_IO04 0xf030
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+ >;
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+ };
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+};
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