llvm/12.0.0: apply ispc recommended patches

ISPC recommends building LLVM 12 with some additional patches to work
around some bugs in this version. Add those patches to our build as well.

https://github.com/ispc/ispc/tree/v1.16.1/llvm_patches

Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0004-ispc-12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch

@@ -0,0 +1,67 @@
+From 0c4ba4947d1630f2e13fc260399f0892b2c9b323 Mon Sep 17 00:00:00 2001
+From: Naveen Saini <naveen.kumar.saini@intel.com>
+Date: Fri, 27 Aug 2021 10:55:13 +0800
+Subject: [PATCH 1/2] This patch is needed for ISPC for Gen only
+
+1. Transformation of add to or is not safe for VC backend.
+2. bswap intrinsics is not supported in VC backend yet.
+
+Upstream-Status: Backport [Taken from ispc, https://github.com/ispc/ispc/blob/v1.16.1/llvm_patches/12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch]
+
+Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
+---
+ llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp  | 10 +++++++---
+ .../lib/Transforms/InstCombine/InstCombineAndOrXor.cpp |  9 ++++++---
+ 2 files changed, 13 insertions(+), 6 deletions(-)
+
+diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+index bacb8689892a..f3d0120db256 100644
+--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
++++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+@@ -15,6 +15,7 @@
+ #include "llvm/ADT/APInt.h"
+ #include "llvm/ADT/STLExtras.h"
+ #include "llvm/ADT/SmallVector.h"
++#include "llvm/ADT/Triple.h"
+ #include "llvm/Analysis/InstructionSimplify.h"
+ #include "llvm/Analysis/ValueTracking.h"
+ #include "llvm/IR/Constant.h"
+@@ -1363,9 +1364,12 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
+     }
+   }
+ 
+-  // A+B --> A|B iff A and B have no bits set in common.
+-  if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
+-    return BinaryOperator::CreateOr(LHS, RHS);
++  // Disable this transformation for ISPC SPIR-V
++  if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
++    // A+B --> A|B iff A and B have no bits set in common.
++    if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
++      return BinaryOperator::CreateOr(LHS, RHS);
++  }
+ 
+   // add (select X 0 (sub n A)) A  -->  select X A n
+   {
+diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+index 68c4156af2c4..b145b863ca84 100644
+--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
++++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
+@@ -2584,9 +2584,12 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
+   if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I))
+     return FoldedLogic;
+ 
+-  if (Instruction *BSwap = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
+-                                                  /*MatchBitReversals*/ false))
+-    return BSwap;
++  // Disable this transformation for ISPC SPIR-V
++  if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
++    if (Instruction *BSwap = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
++                                                    /*MatchBitReversals*/ false))
++      return BSwap;
++  }
+ 
+   if (Instruction *Funnel = matchFunnelShift(I, *this))
+     return Funnel;
+-- 
+2.17.1
+

dynamic-layers/clang-layer/recipes-devtools/clang/files/llvm12-0005-ispc-12_0_fix_for_2111.patch

@@ -0,0 +1,35 @@
+From 913e07ea5acf2148e3748b45ddfe3fac3b2d051c Mon Sep 17 00:00:00 2001
+From: Naveen Saini <naveen.kumar.saini@intel.com>
+Date: Fri, 27 Aug 2021 10:56:57 +0800
+Subject: [PATCH 2/2] This patch is a fix for #2111
+
+It ensures that shuffle is lowered for this particular case correctly.
+
+Upstream-Status: Backport [https://github.com/llvm/llvm-project/commit/9ab99f773fec7da4183495a3fdc655a797d3bea2]
+
+Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
+---
+ llvm/lib/Target/X86/X86ISelLowering.cpp | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
+index 6b816c710f98..3121b0e818ac 100644
+--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
++++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
+@@ -43192,9 +43192,10 @@ static SDValue combineHorizOpWithShuffle(SDNode *N, SelectionDAG &DAG,
+           ShuffleVectorSDNode::commuteMask(ShuffleMask1);
+         }
+         if ((Op00 == Op10) && (Op01 == Op11)) {
+-          SmallVector<int, 4> ShuffleMask;
+-          ShuffleMask.append(ShuffleMask0.begin(), ShuffleMask0.end());
+-          ShuffleMask.append(ShuffleMask1.begin(), ShuffleMask1.end());
++          const int Map[4] = {0, 2, 1, 3};
++          SmallVector<int, 4> ShuffleMask(
++            {Map[ShuffleMask0[0]], Map[ShuffleMask1[0]], Map[ShuffleMask0[1]],
++             Map[ShuffleMask1[1]]});
+           SDLoc DL(N);
+           MVT ShufVT = VT.isFloatingPoint() ? MVT::v4f64 : MVT::v4i64;
+           SDValue Res = DAG.getNode(Opcode, DL, VT, Op00, Op01);
+-- 
+2.17.1
+

dynamic-layers/clang-layer/recipes-devtools/clang/llvm-project-source.bbappend

@@ -34,6 +34,8 @@ SRC_URI_LLVM12_PATCHES = " \
                    file://llvm12-0001-Remove-__IMAGE_SUPPORT__-macro-for-SPIR-since-SPIR-d.patch \
                    file://llvm12-0002-Avoid-calling-ParseCommandLineOptions-in-BackendUtil.patch \
                    file://llvm12-0003-Support-cl_ext_float_atomics.patch \
+                   file://llvm12-0004-ispc-12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch \
+                   file://llvm12-0005-ispc-12_0_fix_for_2111.patch \
                    "