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libva-intel-driver: workaround for concurrent VC1 and H264 playback issue
Explanation from Terence Chiang: "encountered a GFX issue while enabling HW video playback VC-1 and H.264 simultaneously, the graphic driver report error with gfx hang on Sandy Bridge platform. We worked with Intel Linux graphic team and provided a patch" Signed-off-by: Tom Zanussi <tom.zanussi@intel.com>
This commit is contained in:
Tom Zanussi
parent
38685d6522
commit
9615c24f9d
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@ -0,0 +1,440 @@
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Upstream-Status: Pending
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From 43c3fd3ea485a0b9ad12c248a0a94a959ab4d5ee Mon Sep 17 00:00:00 2001
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From: "Xiang, Haihao" <haihao.xiang@intel.com>
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Date: Mon, 29 Oct 2012 10:01:16 +0800
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Subject: [PATCH] Workaround for concurrently playing VC1 and H264 video on SNB
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Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
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---
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src/gen6_mfd.c | 379 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
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src/gen6_mfd.h | 3 +
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2 files changed, 380 insertions(+), 2 deletions(-)
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diff --git a/src/gen6_mfd.c b/src/gen6_mfd.c
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index fa2f128..b8c671b 100755
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--- a/src/gen6_mfd.c
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+++ b/src/gen6_mfd.c
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@@ -50,6 +50,377 @@ static const uint32_t zigzag_direct[64] = {
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53, 60, 61, 54, 47, 55, 62, 63
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};
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+/* Workaround for VC1 decoding */
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+
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+VAStatus
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+i965_DestroySurfaces(VADriverContextP ctx,
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+ VASurfaceID *surface_list,
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+ int num_surfaces);
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+VAStatus
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+i965_CreateSurfaces(VADriverContextP ctx,
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+ int width,
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+ int height,
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+ int format,
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+ int num_surfaces,
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+ VASurfaceID *surfaces);
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+
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+static struct {
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+ int width;
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+ int height;
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+ int mb_count;
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+ unsigned char data[32];
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+ int data_size;
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+ int data_bit_offset;
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+
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+ unsigned int f_code:16;
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+ unsigned int intra_dc_precision:2;
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+ unsigned int picture_structure:2;
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+ unsigned int top_field_first:1;
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+ unsigned int frame_pred_frame_dct:1;
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+ unsigned int concealment_motion_vectors:1;
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+ unsigned int q_scale_type:1;
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+ unsigned int intra_vlc_format:1;
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+ unsigned int alternate_scan:1;
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+ unsigned int picture_coding_type:1;
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+ unsigned int pad0: 5;
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+
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+ unsigned int quantiser_scale_code;
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+
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+ unsigned char qm[2][64];
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+} gen6_dwa_clip = {
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+ width: 32,
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+ height: 16,
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+ mb_count: 2,
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+ data: {
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+ 0x00, 0x00, 0x01, 0x01, 0x1b, 0xfb, 0xfd, 0xf8,
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+ 0x02, 0x97, 0xef, 0xf8, 0x8b, 0x97, 0xe0, 0x0a,
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+ 0x5f, 0xbf, 0xe2, 0x20, 0x00, 0x00, 0x01, 0x00
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+ },
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+ data_size: 20,
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+ data_bit_offset: 38,
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+
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+ f_code: 0xffff,
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+ intra_dc_precision: 0,
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+ picture_structure: 3,
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+ top_field_first: 0,
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+ frame_pred_frame_dct: 1,
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+ concealment_motion_vectors: 0,
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+ q_scale_type: 0,
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+ intra_vlc_format: 0,
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+ alternate_scan: 0,
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+ picture_coding_type: 1, /* I frame */
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+
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+ quantiser_scale_code: 3,
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+
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+ qm: {
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+ {
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+ 8, 16, 19, 22, 26, 27, 29, 34,
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+ 16, 16, 22, 24, 27, 29, 34, 37,
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+ 19, 22, 26, 27, 29, 34, 34, 38,
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+ 22, 22, 26, 27, 29, 34, 37, 40,
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+ 22, 26, 27, 29, 32, 35, 40, 48,
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+ 26, 27, 29, 32, 35, 40, 48, 58,
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+ 26, 27, 29, 34, 38, 46, 56, 69,
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+ 27, 29, 35, 38, 46, 56, 69, 83
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+ },
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+
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+ {
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+ 16, 16, 16, 16, 16, 16, 16, 16,
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+ 16, 16, 16, 16, 16, 16, 16, 16,
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+ 16, 16, 16, 16, 16, 16, 16, 16,
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+ 16, 16, 16, 16, 16, 16, 16, 16,
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+ 16, 16, 16, 16, 16, 16, 16, 16,
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+ 16, 16, 16, 16, 16, 16, 16, 16,
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+ 16, 16, 16, 16, 16, 16, 16, 16,
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+ 16, 16, 16, 16, 16, 16, 16, 16,
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+ }
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+ },
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+};
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+
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+static void
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+gen6_dwa_init(VADriverContextP ctx,
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+ struct gen6_mfd_context *gen6_mfd_context)
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+{
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+ struct i965_driver_data *i965 = i965_driver_data(ctx);
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+ VAStatus status;
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+ struct object_surface *obj_surface;
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+
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+ if (gen6_mfd_context->dwa_surface_id != VA_INVALID_SURFACE)
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+ i965_DestroySurfaces(ctx,
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+ &gen6_mfd_context->dwa_surface_id,
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+ 1);
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+
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+ status = i965_CreateSurfaces(ctx,
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+ gen6_dwa_clip.width,
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+ gen6_dwa_clip.height,
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+ VA_RT_FORMAT_YUV420,
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+ 1,
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+ &gen6_mfd_context->dwa_surface_id);
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+ assert(status == VA_STATUS_SUCCESS);
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+
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+ obj_surface = SURFACE(gen6_mfd_context->dwa_surface_id);
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+ assert(obj_surface);
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+ i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
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+
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+ if (!gen6_mfd_context->dwa_slice_data_bo)
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+ dri_bo_unreference(gen6_mfd_context->dwa_slice_data_bo);
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+
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+ gen6_mfd_context->dwa_slice_data_bo = dri_bo_alloc(i965->intel.bufmgr,
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+ "WA data",
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+ 0x1000,
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+ 0x1000);
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+ dri_bo_subdata(gen6_mfd_context->dwa_slice_data_bo,
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+ 0,
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+ gen6_dwa_clip.data_size,
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+ gen6_dwa_clip.data);
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+}
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+
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+static void
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+gen6_dwa_pipe_mode_select(VADriverContextP ctx,
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+ struct gen6_mfd_context *gen6_mfd_context)
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+{
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+ struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
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+
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+ BEGIN_BCS_BATCH(batch, 4);
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+ OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
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+ OUT_BCS_BATCH(batch,
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+ (MFD_MODE_VLD << 16) | /* VLD mode */
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+ (0 << 10) | /* disable Stream-Out */
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+ (0 << 9) | /* Post Deblocking Output */
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+ (1 << 8) | /* Pre Deblocking Output */
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+ (0 << 7) | /* disable TLB prefectch */
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+ (0 << 5) | /* not in stitch mode */
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+ (MFX_CODEC_DECODE << 4) | /* decoding mode */
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+ (MFX_FORMAT_MPEG2 << 0));
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+ OUT_BCS_BATCH(batch,
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+ (0 << 20) | /* round flag in PB slice */
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+ (0 << 19) | /* round flag in Intra8x8 */
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+ (0 << 7) | /* expand NOA bus flag */
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+ (1 << 6) | /* must be 1 */
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+ (0 << 5) | /* disable clock gating for NOA */
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+ (0 << 4) | /* terminate if AVC motion and POC table error occurs */
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+ (0 << 3) | /* terminate if AVC mbdata error occurs */
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+ (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
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+ (0 << 1) | /* AVC long field motion vector */
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+ (0 << 0)); /* always calculate AVC ILDB boundary strength */
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+ OUT_BCS_BATCH(batch, 0);
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+ ADVANCE_BCS_BATCH(batch);
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+}
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+
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+static void
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+gen6_dwa_surface_state(VADriverContextP ctx,
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+ struct gen6_mfd_context *gen6_mfd_context)
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+{
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+ struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
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+ struct i965_driver_data *i965 = i965_driver_data(ctx);
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+ struct object_surface *obj_surface = SURFACE(gen6_mfd_context->dwa_surface_id);
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+
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+ BEGIN_BCS_BATCH(batch, 6);
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+ OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
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+ OUT_BCS_BATCH(batch, 0);
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+ OUT_BCS_BATCH(batch,
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+ ((obj_surface->orig_width - 1) << 19) |
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+ ((obj_surface->orig_height - 1) << 6));
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+ OUT_BCS_BATCH(batch,
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+ (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
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+ (1 << 27) | /* interleave chroma */
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+ (0 << 22) | /* surface object control state, ignored */
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+ ((obj_surface->width - 1) << 3) | /* pitch */
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+ (0 << 2) | /* must be 0 */
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+ (1 << 1) | /* must be tiled */
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+ (I965_TILEWALK_YMAJOR << 0)); /* tile walk, must be 1 */
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+ OUT_BCS_BATCH(batch,
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+ (0 << 16) | /* X offset for U(Cb), must be 0 */
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+ (obj_surface->y_cb_offset << 0)); /* Y offset for U(Cb) */
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+ OUT_BCS_BATCH(batch,
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+ (0 << 16) | /* X offset for V(Cr), must be 0 */
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+ (0 << 0)); /* Y offset for V(Cr), must be 0 for video codec */
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+ ADVANCE_BCS_BATCH(batch);
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+}
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+
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+static void
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+gen6_dwa_pipe_buf_addr_state(VADriverContextP ctx,
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+ struct gen6_mfd_context *gen6_mfd_context)
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+{
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+ struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
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+ struct i965_driver_data *i965 = i965_driver_data(ctx);
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+ struct object_surface *obj_surface = SURFACE(gen6_mfd_context->dwa_surface_id);
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+ dri_bo *intra_bo;
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+ int i;
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+
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+ intra_bo = dri_bo_alloc(i965->intel.bufmgr,
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+ "intra row store",
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+ 128 * 64,
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+ 0x1000);
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+
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+ BEGIN_BCS_BATCH(batch, 24);
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+ OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
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+ OUT_BCS_RELOC(batch,
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+ obj_surface->bo,
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+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
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+ 0);
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+
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+ OUT_BCS_BATCH(batch, 0); /* post deblocking */
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+
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+ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
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+ OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
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+
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+ OUT_BCS_RELOC(batch,
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+ intra_bo,
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+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
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+ 0);
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+
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+ OUT_BCS_BATCH(batch, 0);
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+
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+ /* DW 7..22 */
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+ for (i = 0; i < MAX_GEN_REFERENCE_FRAMES; i++) {
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+ OUT_BCS_BATCH(batch, 0);
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+ }
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+
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+ OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
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+ ADVANCE_BCS_BATCH(batch);
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+
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+ dri_bo_unreference(intra_bo);
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+}
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+
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+static void
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+gen6_dwa_bsp_buf_base_addr_state(VADriverContextP ctx,
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+ struct gen6_mfd_context *gen6_mfd_context)
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+{
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+ struct i965_driver_data *i965 = i965_driver_data(ctx);
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+ struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
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+ dri_bo *bsd_mpc_bo;
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+
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+ bsd_mpc_bo = dri_bo_alloc(i965->intel.bufmgr,
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+ "bsd mpc row store",
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+ 11520, /* 1.5 * 120 * 64 */
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+ 0x1000);
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+
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+ BEGIN_BCS_BATCH(batch, 4);
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+ OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
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+
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+ OUT_BCS_RELOC(batch,
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+ bsd_mpc_bo,
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+ I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
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+ 0);
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+ OUT_BCS_BATCH(batch, 0);
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+ OUT_BCS_BATCH(batch, 0);
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+ ADVANCE_BCS_BATCH(batch);
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+
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+ dri_bo_unreference(bsd_mpc_bo);
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+}
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+
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+static void
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+gen6_dwa_mpeg2_pic_state(VADriverContextP ctx,
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+ struct gen6_mfd_context *gen6_mfd_context)
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+
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+{
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+ struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
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+ unsigned int width_in_mbs = ALIGN(gen6_dwa_clip.width, 16) / 16;
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+ unsigned int height_in_mbs = ALIGN(gen6_dwa_clip.height, 16) / 16;
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+
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+ BEGIN_BCS_BATCH(batch, 4);
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+ OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (4 - 2));
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+ OUT_BCS_BATCH(batch,
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+ gen6_dwa_clip.f_code << 16 |
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+ gen6_dwa_clip.intra_dc_precision << 14 |
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+ gen6_dwa_clip.picture_structure << 12 |
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+ gen6_dwa_clip.top_field_first << 11 |
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+ gen6_dwa_clip.frame_pred_frame_dct << 10 |
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+ gen6_dwa_clip.concealment_motion_vectors << 9 |
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+ gen6_dwa_clip.q_scale_type << 8 |
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+ gen6_dwa_clip.intra_vlc_format << 7 |
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+ gen6_dwa_clip.alternate_scan << 6);
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+ OUT_BCS_BATCH(batch,
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+ gen6_dwa_clip.picture_coding_type << 9);
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+ OUT_BCS_BATCH(batch,
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+ height_in_mbs << 16 |
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+ width_in_mbs);
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+ ADVANCE_BCS_BATCH(batch);
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+}
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+
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+static void
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+gen6_dwa_mpeg2_qm_state(VADriverContextP ctx,
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+ struct gen6_mfd_context *gen6_mfd_context)
|
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+{
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+ struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
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+ int i;
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+
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+ for (i = 0; i < 2; i++) {
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+ BEGIN_BCS_BATCH(batch, 18);
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+ OUT_BCS_BATCH(batch, MFX_MPEG2_QM_STATE | (18 - 2));
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+ OUT_BCS_BATCH(batch, i);
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+ intel_batchbuffer_data(batch, gen6_dwa_clip.qm[i], 64);
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+ ADVANCE_BCS_BATCH(batch);
|
||||||
|
+ }
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void
|
||||||
|
+gen6_dwa_ind_obj_base_addr_state(VADriverContextP ctx,
|
||||||
|
+ struct gen6_mfd_context *gen6_mfd_context)
|
||||||
|
+{
|
||||||
|
+ struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
|
||||||
|
+
|
||||||
|
+ BEGIN_BCS_BATCH(batch, 11);
|
||||||
|
+ OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
|
||||||
|
+ OUT_BCS_RELOC(batch,
|
||||||
|
+ gen6_mfd_context->dwa_slice_data_bo,
|
||||||
|
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
|
||||||
|
+ 0);
|
||||||
|
+ OUT_BCS_BATCH(batch, 0);
|
||||||
|
+ OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
|
||||||
|
+ OUT_BCS_BATCH(batch, 0);
|
||||||
|
+ OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
|
||||||
|
+ OUT_BCS_BATCH(batch, 0);
|
||||||
|
+ OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
|
||||||
|
+ OUT_BCS_BATCH(batch, 0);
|
||||||
|
+ OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
|
||||||
|
+ OUT_BCS_BATCH(batch, 0);
|
||||||
|
+ ADVANCE_BCS_BATCH(batch);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void
|
||||||
|
+gen6_dwa_mpeg2_bsd_object(VADriverContextP ctx,
|
||||||
|
+ struct gen6_mfd_context *gen6_mfd_context)
|
||||||
|
+{
|
||||||
|
+ struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
|
||||||
|
+
|
||||||
|
+ BEGIN_BCS_BATCH(batch, 5);
|
||||||
|
+ OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
|
||||||
|
+ OUT_BCS_BATCH(batch,
|
||||||
|
+ gen6_dwa_clip.data_size - (gen6_dwa_clip.data_bit_offset >> 3));
|
||||||
|
+ OUT_BCS_BATCH(batch, gen6_dwa_clip.data_bit_offset >> 3);
|
||||||
|
+ OUT_BCS_BATCH(batch,
|
||||||
|
+ (0 << 24) |
|
||||||
|
+ (0 << 16) |
|
||||||
|
+ (gen6_dwa_clip.mb_count << 8) |
|
||||||
|
+ (1 << 5) |
|
||||||
|
+ (1 << 3) |
|
||||||
|
+ (gen6_dwa_clip.data_bit_offset & 0x7));
|
||||||
|
+ OUT_BCS_BATCH(batch,
|
||||||
|
+ gen6_dwa_clip.quantiser_scale_code << 24);
|
||||||
|
+ ADVANCE_BCS_BATCH(batch);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+static void
|
||||||
|
+gen6_mfd_dwa(VADriverContextP ctx,
|
||||||
|
+ struct gen6_mfd_context *gen6_mfd_context)
|
||||||
|
+{
|
||||||
|
+ struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
|
||||||
|
+ gen6_dwa_init(ctx, gen6_mfd_context);
|
||||||
|
+ intel_batchbuffer_emit_mi_flush(batch);
|
||||||
|
+ gen6_dwa_pipe_mode_select(ctx, gen6_mfd_context);
|
||||||
|
+ gen6_dwa_surface_state(ctx, gen6_mfd_context);
|
||||||
|
+ gen6_dwa_pipe_buf_addr_state(ctx, gen6_mfd_context);
|
||||||
|
+ gen6_dwa_bsp_buf_base_addr_state(ctx, gen6_mfd_context);
|
||||||
|
+ gen6_dwa_mpeg2_qm_state(ctx, gen6_mfd_context);
|
||||||
|
+ gen6_dwa_mpeg2_pic_state(ctx, gen6_mfd_context);
|
||||||
|
+ gen6_dwa_ind_obj_base_addr_state(ctx, gen6_mfd_context);
|
||||||
|
+ gen6_dwa_mpeg2_bsd_object(ctx, gen6_mfd_context);
|
||||||
|
+}
|
||||||
|
+
|
||||||
|
+/* end of workaround */
|
||||||
|
+
|
||||||
|
static void
|
||||||
|
gen6_mfd_avc_frame_store_index(VADriverContextP ctx,
|
||||||
|
VAPictureParameterBufferH264 *pic_param,
|
||||||
|
@@ -1055,7 +1426,8 @@ gen6_mfd_avc_decode_picture(VADriverContextP ctx,
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
- gen6_mfd_avc_phantom_slice(ctx, pic_param, gen6_mfd_context);
|
||||||
|
+ gen6_mfd_dwa(ctx, gen6_mfd_context);
|
||||||
|
+
|
||||||
|
intel_batchbuffer_end_atomic(batch);
|
||||||
|
intel_batchbuffer_flush(batch);
|
||||||
|
}
|
||||||
|
@@ -1944,6 +2316,8 @@ gen6_mfd_vc1_decode_picture(VADriverContextP ctx,
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
+ gen6_mfd_dwa(ctx, gen6_mfd_context);
|
||||||
|
+
|
||||||
|
intel_batchbuffer_end_atomic(batch);
|
||||||
|
intel_batchbuffer_flush(batch);
|
||||||
|
}
|
||||||
|
@@ -2031,6 +2405,7 @@ gen6_dec_hw_context_init(VADriverContextP ctx, VAProfile profile)
|
||||||
|
}
|
||||||
|
|
||||||
|
gen6_mfd_context->wa_mpeg2_slice_vertical_position = -1;
|
||||||
|
-
|
||||||
|
+ gen6_mfd_context->dwa_surface_id = VA_INVALID_ID;
|
||||||
|
+
|
||||||
|
return (struct hw_context *)gen6_mfd_context;
|
||||||
|
}
|
||||||
|
diff --git a/src/gen6_mfd.h b/src/gen6_mfd.h
|
||||||
|
index de131d6..7c4a619 100644
|
||||||
|
--- a/src/gen6_mfd.h
|
||||||
|
+++ b/src/gen6_mfd.h
|
||||||
|
@@ -72,6 +72,9 @@ struct gen6_mfd_context
|
||||||
|
GenBuffer bitplane_read_buffer;
|
||||||
|
|
||||||
|
int wa_mpeg2_slice_vertical_position;
|
||||||
|
+
|
||||||
|
+ VASurfaceID dwa_surface_id;
|
||||||
|
+ dri_bo *dwa_slice_data_bo;
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif /* _GEN6_MFD_H_ */
|
||||||
|
--
|
||||||
|
1.7.9.5
|
||||||
|
|
||||||
|
|
@ -4,5 +4,7 @@ PR = "${INC_PR}.0"
|
||||||
|
|
||||||
SRC_URI = "http://www.freedesktop.org/software/vaapi/releases/libva-intel-driver/libva-intel-driver-${PV}.tar.bz2"
|
SRC_URI = "http://www.freedesktop.org/software/vaapi/releases/libva-intel-driver/libva-intel-driver-${PV}.tar.bz2"
|
||||||
|
|
||||||
|
SRC_URI += "file://0001-Workaround-for-concurrently-playing-VC1-and-H264-vid.patch"
|
||||||
|
|
||||||
SRC_URI[md5sum] = "13907085223d88d956cdfc282962b7a7"
|
SRC_URI[md5sum] = "13907085223d88d956cdfc282962b7a7"
|
||||||
SRC_URI[sha256sum] = "789fa2d6e22b9028ce12a89981eb33e57b04301431415149acfb61a49d3a63ee"
|
SRC_URI[sha256sum] = "789fa2d6e22b9028ce12a89981eb33e57b04301431415149acfb61a49d3a63ee"
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue
Block a user