Patches applied from Open PR#171, in order to build with llvm-12.
https://github.com/intel/intel-graphics-compiler/pull/171
Error logs:
(1)
|
/build/tmp/work/corei7-64-poky-linux/intel-graphics-compiler/1.0.6410-r0/git/IGC/Compiler/CISACodeGen/VariableReuseAnalysis.hpp:83:56:
error: 'unsigned int llvm::VectorType::getNumElements() const' is
deprecated: Calling this function via a base VectorType is deprecated.
Either call getElementCount() and handle the case where Scalable is true
or cast to FixedVectorType. [-Werror=deprecated-declarations]
| 83 | NumElts = VTy ? (short)VTy->getNumElements() : 1;
Ref:867de151a5
(2)
|
/build/tmp/work/corei7-64-poky-linux/intel-graphics-compiler/1.0.6410-r0/git/IGC/common/igc_resourceDimTypes.h:69:23:
error: 'const class llvm::Module' has no member named 'getTypeByName'
| 69 | return
module.getTypeByName(ResourceDimensionTypeName[resourceDimTypeId]);
Ref:
fe43168348
Update copyright year in headers in IGC Compiler and some format updates.
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
Build opencl-clang with llvm-12 and point to latest from ocl-open-120
branch.
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
meta-clang now builds llvm-spiv-translator as an external project for
llvm12 so stop building it.
It still need to be built for llvm-10 and llvm-11 though.
Ref:
aa1ab889bc
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
Refreshed patch.
Drop VectorCompiler build config, which is not require anymore.
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
It includes:
77974f5 Wrap getTypeByName() to build with ToT LLVM
2de2dd4 Mangle intrinsic names
017cfcd Added predication for genx_masked_gather.
5032643 Add gather4_masked_scaled2 and gather_masked_scaled2 intrinsics
a08fe5b Add internal llvm.genx.gaddr intrinsic for constant/global table
support
cf29e35 use a more strict version of cast operation in lowerUnmaskOps
d2a2184 Use standard installation directory variables
7cbfe2e Allow OCL types without address convert in reader
410f50d Fix twice application of writer adaptor
e42097e Add GENX_REWRITE_SEV environment variable for debug
ca68b87 Rewrite single element vectors before spirv
008db27 Removing some whitespaces
3b2b67f Correct docs on gather/scatter scaled instructions
9bba8b5 Delete legacy intrinsics
d684443 Add Instructions.h to llvmVCWrapper Add getNumElements func to
llvmVCWrapper
4d724e3 CMCallable attribute conversion in AdaptorCM
73b335b Add Alignment.h to llvmVCWrapper
04d4900 Ignore non-vc kernels in reader type translation
b3f075d Remove SPIRVMemoryModel setting in GenXSPIRVWriterAdaptor
eabcd20 Add jump_table intrinsic
82711ce Fix to make lit tests pass for llvm7: forward isVolatile arg
explicitly when creating load/store
6506440 add missing default initializer to CMSimdCFLower member
9a03e3e Fix for problem with incorrect MD in LLVM IR
4515d60 avoid returning potentially-unitialized value
414153d Fix for wrr predication if new value is a result of a bitcast
77974f5 (HEAD -> master, origin/master, origin/HEAD) Wrap
getTypeByName() to build with ToT LLVM
2de2dd4 Mangle intrinsic names
017cfcd Added predication for genx_masked_gather.
5032643 Add gather4_masked_scaled2 and gather_masked_scaled2 intrinsics
a08fe5b Add internal llvm.genx.gaddr intrinsic for constant/global table
support
cf29e35 use a more strict version of cast operation in lowerUnmaskOps
d2a2184 Use standard installation directory variables
7cbfe2e Allow OCL types without address convert in reader
410f50d Fix twice application of writer adaptor
e42097e Add GENX_REWRITE_SEV environment variable for debug
ca68b87 Rewrite single element vectors before spirv
008db27 Removing some whitespaces
3b2b67f Correct docs on gather/scatter scaled instructions
9bba8b5 Delete legacy intrinsics
d684443 Add Instructions.h to llvmVCWrapper Add getNumElements func to
llvmVCWrapper
4d724e3 CMCallable attribute conversion in AdaptorCM
73b335b Add Alignment.h to llvmVCWrapper
04d4900 Ignore non-vc kernels in reader type translation
b3f075d Remove SPIRVMemoryModel setting in GenXSPIRVWriterAdaptor
eabcd20 Add jump_table intrinsic
82711ce Fix to make lit tests pass for llvm7: forward isVolatile arg
explicitly when creating load/store
6506440 add missing default initializer to CMSimdCFLower member
9a03e3e Fix for problem with incorrect MD in LLVM IR
4515d60 avoid returning potentially-unitialized value
414153d Fix for wrr predication if new value is a result of a bitcast
23d4b41 Add SPIRV writer adaptor types translation
9eda835 Deduced number of channels under SIMD CFG for functions which
use genx_replicate_mask attribute
3b3f9d9 Add llvm version to test features
e13f274 Fix wrong address space for sampler type in reader
5829ad6 Fix missing compatibility with old translator in
GenXSPIRVReaderAdaptor.cpp
3a287f5 Add GetOldStyleKernelMD function to GenXMetadata.h
60dec9a Uniform GenXMetadata.h with AdaptorsCommon.h
ec7de0b Move SPIRV-specific parameters to AdaptorsCommon.h
b869876 Use consume_front in SPIRV reader adaptor
2bb7a70 Fix SPIRV reader adaptor mistranslation of non-global pointers
40db2bb Add SPIRV reader adaptor types translation
65b7d2b Add more correct wrapper for global value address space
2e496ce Synchronize repository
Drop patch, which is already merged and avaialble.
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
This reverts commit 3cf8482e43.
The issues have since been fixed upstream and the tree has been
restored.
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
IGC has a copy of legacy spirv translator and additional
patcheset to produce spirv shared object (libSPIRVDLL.so) to
support Vector compiler.
But we build spirv externally and link, which does not provide spirv
shared object (libSPIRVDLL.so).
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
Fixes errors seen when multilib is turned on
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
Include compatibility for both LLVM 10 and LLVM 11. Vector Compiler
fails to compile for LLVM 11 so disable the build for now.
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
Point to latest for llvm 11 branch as there's no official release yet.
And, pick the version of opencl-clang based on LLVMVERSION.
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
Ensure that we can build with both dunfell (LLVM10) and current master
(LLVM11) of meta-clang. Look for LLVMVERSION set by meta-clang and
include relevant patches based on the version.
There's no official release for SPIRV-LLVM-Translator yet for LLVM11 so
pick the latest.
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
Improve the reproducibility of intel-graphics-compiler-src by replacing
the absolute build path with relative one in bison compiled files.
The --file-prefix-map could only work on bison 3.7 onward so add it only
when bison is newer than 3.7.
│ │ │ -#ifndef
YY_CISA_YOCTO_POKY_MASTER_BUILD_TMP_WORK_SKYLAKE_64_POKY_LINUX_INTEL_GRAPHICS_COMPILER_1_0_4241_R0_BUILD_IGC_VISA_CISA_TAB_HPP_INCLUDED
│ │ │ -# define
YY_CISA_YOCTO_POKY_MASTER_BUILD_TMP_WORK_SKYLAKE_64_POKY_LINUX_INTEL_GRAPHICS_COMPILER_1_0_4241_R0_BUILD_IGC_VISA_CISA_TAB_HPP_INCLUDED
│ │ │ +#ifndef
YY_CISA_YOCTO_POKY_MASTER_BUILD_2_TMP_WORK_SKYLAKE_64_POKY_LINUX_INTEL_GRAPHICS_COMPILER_1_0_4241_R0_BUILD_IGC_VISA_CISA_TAB_HPP_INCLUDED
│ │ │ +# define
YY_CISA_YOCTO_POKY_MASTER_BUILD_2_TMP_WORK_SKYLAKE_64_POKY_LINUX_INTEL_GRAPHICS_COMPILER_1_0_4241_R0_BUILD_IGC_VISA_CISA_TAB_HPP_INCLUDED
Also suppress #line directives in scanner that have the build path:
│ │ │ -#line 2593
"/yocto/poky-master/build/tmp/work/skylake-64-poky-linux/intel-graphics-compiler/1.0.4241-r0/build/IGC/visa/lex.CISA.cpp"
│ │ │ +#line 2593
"/yocto/poky-master/build-2/tmp/work/skylake-64-poky-linux/intel-graphics-compiler/1.0.4241-r0/build/IGC/visa/lex.CISA.cpp"
Signed-off-by: Lee Chee Yang <chee.yang.lee@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
This reverts commit c6ca760d24.
This breaks builds using meta-intel master with oe-core dunfell because
the bison option isn't available on older versions.
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
VC Intrinsics project contains a set of new intrinsics on top of core
LLVM IR instructions that represent SIMD semantics of a program
targeting GPU.
Ref:
https://github.com/intel/vc-intrinsics
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
NOTICES.txt is updated and refactored. Added below:
Khronos Group - SPIRV-LLVM License
Khronos Group OpenCL Registry License
Dropped patch, which is not required anymore.
Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
