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ISPC recommends building LLVM 12 with some additional patches to work around some bugs in this version. Add those patches to our build as well. https://github.com/ispc/ispc/tree/v1.16.1/llvm_patches Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com> Signed-off-by: Anuj Mittal <anuj.mittal@intel.com>
68 lines
2.9 KiB
Diff
68 lines
2.9 KiB
Diff
From 0c4ba4947d1630f2e13fc260399f0892b2c9b323 Mon Sep 17 00:00:00 2001
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From: Naveen Saini <naveen.kumar.saini@intel.com>
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Date: Fri, 27 Aug 2021 10:55:13 +0800
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Subject: [PATCH 1/2] This patch is needed for ISPC for Gen only
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1. Transformation of add to or is not safe for VC backend.
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2. bswap intrinsics is not supported in VC backend yet.
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Upstream-Status: Backport [Taken from ispc, https://github.com/ispc/ispc/blob/v1.16.1/llvm_patches/12_0_disable-A-B-A-B-and-BSWAP-in-InstCombine.patch]
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Signed-off-by: Naveen Saini <naveen.kumar.saini@intel.com>
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---
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llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | 10 +++++++---
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.../lib/Transforms/InstCombine/InstCombineAndOrXor.cpp | 9 ++++++---
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2 files changed, 13 insertions(+), 6 deletions(-)
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diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
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index bacb8689892a..f3d0120db256 100644
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--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
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+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
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@@ -15,6 +15,7 @@
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallVector.h"
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+#include "llvm/ADT/Triple.h"
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#include "llvm/Analysis/InstructionSimplify.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/IR/Constant.h"
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@@ -1363,9 +1364,12 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
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}
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}
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- // A+B --> A|B iff A and B have no bits set in common.
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- if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
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- return BinaryOperator::CreateOr(LHS, RHS);
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+ // Disable this transformation for ISPC SPIR-V
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+ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
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+ // A+B --> A|B iff A and B have no bits set in common.
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+ if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
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+ return BinaryOperator::CreateOr(LHS, RHS);
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+ }
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// add (select X 0 (sub n A)) A --> select X A n
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{
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diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
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index 68c4156af2c4..b145b863ca84 100644
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--- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
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+++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
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@@ -2584,9 +2584,12 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) {
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if (Instruction *FoldedLogic = foldBinOpIntoSelectOrPhi(I))
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return FoldedLogic;
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- if (Instruction *BSwap = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
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- /*MatchBitReversals*/ false))
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- return BSwap;
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+ // Disable this transformation for ISPC SPIR-V
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+ if (!Triple(I.getModule()->getTargetTriple()).isSPIR()) {
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+ if (Instruction *BSwap = matchBSwapOrBitReverse(I, /*MatchBSwaps*/ true,
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+ /*MatchBitReversals*/ false))
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+ return BSwap;
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+ }
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if (Instruction *Funnel = matchFunnelShift(I, *this))
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return Funnel;
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--
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2.17.1
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