Saul Wold afbba3222c linux-yocto_3.19: Update to the Intel i915 driver ... 0befa35 drm/i915/chv: Remove DPIO force latency causing interpair skew issue 184e037 drm/i915: Fix chv cdclk support e2a99b9 drm/i915: Increase the range of sideband address. 9d5d55e drm/i915: Disable DDR DVFS on CHV 96cce94 drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV b5005319 drm/i915: Program PFI credits for VLV c7aa33e drm/i915: Rewrite VLV/CHV watermark code a421d8b drm/i915: Make sure PND deadline mode is enabled on VLV/CHV 631afc9 drm/i915: Read out display FIFO size on VLV/CHV e0dcdc0 drm/i915: Pass plane to vlv_compute_drain_latency() a6a5562 drm/i915: Reorganize VLV DDL setup bb662a4 drm/i915: Hide VLV DDL precision handling 3d2d932 drm/i915: Simplify VLV drain latency computation f686147 drm/i915: Kill DRAIN_LATENCY_PRECISION_* defines 86c658c drm/i915: Reduce CHV DDL multiplier to 16/8 8c4cdd9 drm/i915: Allow pixel clock up to 95% of cdclk on CHV d9d4fb8 drm/i915: Reduce CHV DPLL min vco frequency to 4.8 GHz Signed-off-by: Saul Wold <sgw@linux.intel.com>		2015-05-11 11:18:41 -07:00
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custom-licenses	Remove all the changes related to the proprietary EMGD graphics driver	2014-09-16 20:12:28 -05:00
recipes-bsp	lms7: re-write do_unpack to fix warning	2015-04-15 15:07:52 -07:00
recipes-core/microcode	intel-microcode: Mark as x86-specific	2015-01-07 09:13:12 -06:00
recipes-corpus	calgary-corpus: inherit allarch	2014-05-21 20:22:01 -05:00
recipes-graphics	xf86-video-mga: Upgrade 1.6.2 -> 1.6.4	2015-05-07 13:12:20 -07:00
recipes-kernel/linux	linux-yocto_3.19: Update to the Intel i915 driver	2015-05-11 11:18:41 -07:00
recipes-multimedia	gst-va-intel: remove	2015-02-27 15:21:44 -08:00