Add RISCV32/64 support

Upstream-Status: Pending

Signed-off-by: Andreas Müller <schnitzeltony@gmail.com>
---
 build/moz.configure/init.configure                        | 6 ++++++
 python/mozbuild/mozbuild/configure/constants.py           | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/build/moz.configure/init.configure b/build/moz.configure/init.configure
index 0a6a33c..eeee87e 100644
--- a/build/moz.configure/init.configure
+++ b/build/moz.configure/init.configure
@@ -755,6 +755,12 @@ def split_triplet(triplet, allow_msvc=False):
     elif cpu.startswith('aarch64'):
         canonical_cpu = 'aarch64'
         endianness = 'little'
+    elif cpu in ("riscv32", "riscv32gc"):
+        canonical_cpu = "riscv32"
+        endianness = "little"
+    elif cpu in ("riscv64", "riscv64gc"):
+        canonical_cpu = "riscv64"
+        endianness = "little"
     elif cpu == 'sh4':
         canonical_cpu = 'sh4'
         endianness = 'little'
diff --git a/python/mozbuild/mozbuild/configure/constants.py b/python/mozbuild/mozbuild/configure/constants.py
index 7542dcd..de25be2 100644
--- a/python/mozbuild/mozbuild/configure/constants.py
+++ b/python/mozbuild/mozbuild/configure/constants.py
@@ -50,6 +50,8 @@ CPU_bitness = {
     'mips64': 64,
     'ppc': 32,
     'ppc64': 64,
+    'riscv32': 32,
+    'riscv64': 64,
     's390': 32,
     's390x': 64,
     'sh4': 32,
@@ -82,6 +84,8 @@ CPU_preprocessor_checks = OrderedDict((
     ('s390', '__s390__'),
     ('ppc64', '__powerpc64__'),
     ('ppc', '__powerpc__'),
+    ('riscv32', '__riscv && __SIZEOF_POINTER__ == 4'),
+    ('riscv64', '__riscv && __SIZEOF_POINTER__ == 8'),
     ('Alpha', '__alpha__'),
     ('hppa', '__hppa__'),
     ('sparc64', '__sparc__ && __arch64__'),
-- 
2.31.1

