python3-grpcio: Update to 1.38.0

Drop riscv patch as its applied upstream
Refresh patches

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Trevor Gamblin <trevor.gamblin@windriver.com>
This commit is contained in:
Khem Raj 2021-05-29 00:34:56 -07:00
parent a603cfc4dd
commit b3375a4adc
3 changed files with 2 additions and 25 deletions

View File

@ -12,4 +12,4 @@
+#elif defined(__mips__) && defined(__LP64__)
#define OPENSSL_64_BIT
#define OPENSSL_MIPS64
#elif defined(__riscv)
#elif defined(__riscv) && __SIZEOF_POINTER__ == 8

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@ -1,21 +0,0 @@
Add RISC-V 64bit support
Upstream-Status: Pending
Signed-off-by: Khem Raj <raj.khem@gmail.com>
--- a/third_party/boringssl-with-bazel/src/include/openssl/base.h
+++ b/third_party/boringssl-with-bazel/src/include/openssl/base.h
@@ -108,6 +108,14 @@ extern "C" {
#elif defined(__MIPSEL__) && defined(__LP64__)
#define OPENSSL_64_BIT
#define OPENSSL_MIPS64
+#elif defined(__riscv)
+# if (__riscv_xlen == 64)
+# define OPENSSL_64_BIT
+# define OPENSSL_RISCV64
+# elif(__riscv_xlen == 32)
+# define OPENSSL_32_BIT
+# define OPENSSL_RISCV32
+# endif
#elif defined(__pnacl__)
#define OPENSSL_32_BIT
#define OPENSSL_PNACL

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@ -8,12 +8,11 @@ DEPENDS += "${PYTHON_PN}-protobuf"
SRC_URI += "file://0001-setup.py-Do-not-mix-C-and-C-compiler-options.patch"
SRC_URI_append_class-target = " file://ppc-boringssl-support.patch \
file://riscv64_support.patch \
file://boring_ssl.patch \
file://mips_bigendian.patch \
file://0001-absl-always-use-asm-sgidefs.h.patch \
"
SRC_URI[sha256sum] = "b3ce16aa91569760fdabd77ca901b2288152eb16941d28edd9a3a75a0c4a8a85"
SRC_URI[sha256sum] = "abbf9c8c3df4d5233d5888c6cfa85c1bb68a6923749bd4dd1abc6e1e93986f17"
RDEPENDS_${PN} = "${PYTHON_PN}-protobuf \
${PYTHON_PN}-setuptools \
@ -46,4 +45,3 @@ CCACHE_DISABLE = "1"
# needs vdso support
COMPATIBLE_HOST_libc-musl_powerpc64le = "null"