meta-openembedded/meta-python/recipes-devtools/python/python3-pyruvate/0001-riscv64-mod.rs-Add-missing-error-codes.patch
Khem Raj 1cf791b208 python3-pyruvate: Fix build on riscv32
refresh upstream status as needed.

Signed-off-by: Khem Raj <raj.khem@gmail.com>
Signed-off-by: Trevor Gamblin <trevor.gamblin@windriver.com>
2022-03-09 07:37:03 -08:00

33 lines
1.2 KiB
Diff

From a6f5bb3e7fe51733144497a3b5962b300f922a2d Mon Sep 17 00:00:00 2001
From: Khem Raj <raj.khem@gmail.com>
Date: Mon, 7 Mar 2022 11:02:46 -0800
Subject: [PATCH] riscv64/mod.rs: Add missing error codes
These are flagged by apps e.g. python3-pyruvate
Upstream-Status: Backport [https://github.com/rust-lang/libc/commit/c711fb215de54f960a35cdc48cd506b6b5db4918]
Signed-off-by: Khem Raj <raj.khem@gmail.com>
---
src/unix/linux_like/linux/musl/b64/riscv64/mod.rs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/unix/linux_like/linux/musl/b64/riscv64/mod.rs b/src/unix/linux_like/linux/musl/b64/riscv64/mod.rs
index 48fee4e..7c88abe 100644
--- a/src/unix/linux_like/linux/musl/b64/riscv64/mod.rs
+++ b/src/unix/linux_like/linux/musl/b64/riscv64/mod.rs
@@ -551,6 +551,11 @@ pub const EHOSTUNREACH: ::c_int = 113;
pub const EALREADY: ::c_int = 114;
pub const EINPROGRESS: ::c_int = 115;
pub const ESTALE: ::c_int = 116;
+pub const EUCLEAN: ::c_int = 117;
+pub const ENOTNAM: ::c_int = 118;
+pub const ENAVAIL: ::c_int = 119;
+pub const EISNAM: ::c_int = 120;
+pub const EREMOTEIO: ::c_int = 121;
pub const EDQUOT: ::c_int = 122;
pub const ENOMEDIUM: ::c_int = 123;
pub const EMEDIUMTYPE: ::c_int = 124;
--
2.35.1