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3c5c4cfa6b
This implements the following base ISAs: * rv32i, rv64i * rv32e, rv64i The following ABIs: * ilp32, ilp32e, ilp32f, ilp32d * lp64, lp64e, lp64f, lp64d The following ISA extension are also implemented: * M - Integer Multiplication and Division Extension * A - Atomic Memory Extension * F - Single-Precision Floating-Point Extension * D - Double-Precision Floating-Point Extension * C - Compressed Extension * B - Bit Manipulation Extension (implies Zba, Zbb, Zbs) * V - Vector Operations Extension * Zicsr - Control and Status Register Access Extension * Zifencei - Instruction-Fetch Fence Extension * Zba - Address bit manipulation extension * Zbb - Basic bit manipulation extension * Zbc - Carry-less multiplication extension * Zbs - Single-bit manipulation extension * Zicbom - Cache-block management extension The existing processors tunes are preserved: * riscv64 (rv64gc) * riscv32 (rv32gc) * riscv64nf (rv64imac_zicsr_zifencei) * riscv32nf (rv32imac_zicsr_zifencei) * riscv64nc (rv64imafd_zicsr_zifencei) Previously defined feature 'big-endian' has been removed as it was not used. (From OE-Core rev: bcaf298a146dfd10e4c8f44223ea083bc4baf45c) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
16 lines
564 B
Python
16 lines
564 B
Python
#
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# Copyright OpenEmbedded Contributors
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#
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# SPDX-License-Identifier: GPL-2.0-only
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#
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from pkgutil import extend_path
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__path__ = extend_path(__path__, __name__)
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# Modules with vistorcode need to go first else anything depending on them won't be
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# processed correctly (e.g. qa)
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BBIMPORTS = ["qa", "data", "path", "utils", "types", "package", "packagedata", \
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"packagegroup", "sstatesig", "lsb", "cachedpath", "license", "qemu", \
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"reproducible", "rust", "buildcfg", "go", "spdx30_tasks", "spdx_common", \
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"cve_check", "tune"]
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