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MA-22424-2: mxc: vpu: vc8000e: Use fixed-length types in ioctl parameters
To support 32bit application, we should use fixed-length types in ioctl parameters, specifically avoid using the type long and unsigned long. remove some unused ioctl cmd. clear some building warning. Signed-off-by: Ming Qian <ming.qian@nxp.com> Reviewed-by: TaoJiang <tao.jiang_2@nxp.com>
This commit is contained in:
Ming Qian
parent
08d3e59a62
commit
b305ce6758
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@ -65,22 +65,17 @@
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* #define HX280ENC_IOCGBUFBUSADDRESS _IOR(HX280ENC_IOC_MAGIC, 1, unsigned long *)
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* #define HX280ENC_IOCGBUFSIZE _IOR(HX280ENC_IOC_MAGIC, 2, unsigned int *)
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*/
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#define HX280ENC_IOCGHWOFFSET _IOR(HX280ENC_IOC_MAGIC, 3, unsigned long *)
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#define HX280ENC_IOCGHWIOSIZE _IOR(HX280ENC_IOC_MAGIC, 4, unsigned int *)
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#define HX280ENC_IOC_CLI _IO(HX280ENC_IOC_MAGIC, 5)
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#define HX280ENC_IOC_STI _IO(HX280ENC_IOC_MAGIC, 6)
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#define HX280ENC_IOCXVIRT2BUS _IOWR(HX280ENC_IOC_MAGIC, 7, unsigned long *)
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#define HX280ENC_IOCGHWOFFSET _IOR(HX280ENC_IOC_MAGIC, 3, u32 *)
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#define HX280ENC_IOCGHWIOSIZE _IOR(HX280ENC_IOC_MAGIC, 4, u32 *)
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#define HX280ENC_IOCHARDRESET _IO(HX280ENC_IOC_MAGIC, 8) /* debugging tool */
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#define HX280ENC_IOCGSRAMOFFSET _IOR(HX280ENC_IOC_MAGIC, 9, u32 *)
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#define HX280ENC_IOCGSRAMEIOSIZE _IOR(HX280ENC_IOC_MAGIC, 10, u32 *)
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#define HX280ENC_IOCH_ENC_RESERVE _IOR(HX280ENC_IOC_MAGIC, 11, u32 *)
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#define HX280ENC_IOCH_ENC_RELEASE _IOR(HX280ENC_IOC_MAGIC, 12, u32 *)
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#define HX280ENC_IOCG_CORE_NUM _IOR(HX280ENC_IOC_MAGIC, 13, u32 *)
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#define HX280ENC_IOCG_EN_CORE _IOR(HX280ENC_IOC_MAGIC, 14, u32 *)
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#define HX280ENC_IOCGSRAMOFFSET _IOR(HX280ENC_IOC_MAGIC, 9, unsigned long *)
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#define HX280ENC_IOCGSRAMEIOSIZE _IOR(HX280ENC_IOC_MAGIC, 10, unsigned int *)
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#define HX280ENC_IOCH_ENC_RESERVE _IOR(HX280ENC_IOC_MAGIC, 11, unsigned int *)
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#define HX280ENC_IOCH_ENC_RELEASE _IOR(HX280ENC_IOC_MAGIC, 12, unsigned int *)
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#define HX280ENC_IOCG_CORE_NUM _IOR(HX280ENC_IOC_MAGIC, 13, unsigned int *)
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#define HX280ENC_IOCG_EN_CORE _IOR(HX280ENC_IOC_MAGIC, 14, unsigned int *)
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#define HX280ENC_IOCG_CORE_WAIT _IOR(HX280ENC_IOC_MAGIC, 19, unsigned int *)
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#define HX280ENC_IOCG_CORE_WAIT _IOR(HX280ENC_IOC_MAGIC, 19, u32 *)
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#define HX280ENC_IOC_WRITE_REGS _IOW(HX280ENC_IOC_MAGIC, 20, struct enc_regs_buffer *)
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#define HX280ENC_IOC_READ_REGS _IOR(HX280ENC_IOC_MAGIC, 21, struct enc_regs_buffer *)
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@ -73,7 +73,7 @@ static bool hantro_skip_blkctrl;
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/********variables declaration related with race condition**********/
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struct semaphore enc_core_sem;
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static struct semaphore enc_core_sem;
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static DECLARE_WAIT_QUEUE_HEAD(hw_queue);
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static DEFINE_SPINLOCK(owner_lock);
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static DECLARE_WAIT_QUEUE_HEAD(enc_wait_queue);
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@ -93,7 +93,7 @@ static DECLARE_WAIT_QUEUE_HEAD(enc_wait_queue);
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/*for all cores, the core info should be listed here for subsequent use*/
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/*base_addr, iosize, irq, resource_shared*/
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CORE_CONFIG core_array[] = {
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static CORE_CONFIG core_array[] = {
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{CORE_0_IO_ADDR, CORE_0_IO_SIZE, INT_PIN_CORE_0, RESOURCE_SHARED_INTER_CORES}, //core_0 (VC8000E)
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//{CORE_1_IO_ADDR, CORE_1_IO_SIZE, INT_PIN_CORE_1, RESOURCE_SHARED_INTER_CORES} //core_1 (VC8000EJ)
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};
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@ -114,7 +114,7 @@ typedef struct {
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u32 irq_status;
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char *buffer;
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unsigned int buffsize;
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volatile u8 *hwregs;
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void __iomem *hwregs;
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u32 reg_buf[CORE_0_IO_SIZE/4];
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struct semaphore core_suspend_sem;
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u32 reg_corrupt;
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@ -178,7 +178,7 @@ static int hantro_vc8000e_clk_disable(struct device *dev)
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static int hantro_vc8000e_ctrlblk_reset(struct device *dev)
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{
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volatile u8 *iobase;
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void __iomem *iobase;
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u32 val;
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if (hantro_skip_blkctrl)
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@ -186,7 +186,7 @@ static int hantro_vc8000e_ctrlblk_reset(struct device *dev)
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//config vc8000e
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hantro_vc8000e_clk_enable(dev);
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iobase = (volatile u8 *)ioremap(BLK_CTL_BASE, 0x10000);
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iobase = ioremap(BLK_CTL_BASE, 0x10000);
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val = ioread32(iobase);
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val &= (~0x4);
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@ -422,7 +422,7 @@ static int hantroenc_write_regs(struct enc_regs_buffer *regs)
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dev = &hantroenc_data[regs->core_id];
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reg_buf = &dev->reg_buf[regs->offset / 4];
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ret = copy_from_user(reg_buf, (void *)regs->regs, regs->size);
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ret = copy_from_user(reg_buf, (void __user *)regs->regs, regs->size);
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if (ret)
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return ret;
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@ -456,7 +456,7 @@ static int hantroenc_read_regs(struct enc_regs_buffer *regs)
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for (i = 0; i < regs->size / 4; i++)
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reg_buf[i] = ioread32((dev->hwregs + regs->offset) + i * 4);
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ret = copy_to_user((void *)regs->regs, reg_buf, regs->size);
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ret = copy_to_user((void __user *)regs->regs, reg_buf, regs->size);
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return ret;
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}
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@ -494,9 +494,9 @@ static long hantroenc_ioctl(struct file *filp,
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* "write" is reversed
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*/
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if (_IOC_DIR(cmd) & _IOC_READ)
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err = !access_ok((void *) arg, _IOC_SIZE(cmd));
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err = !access_ok((void __user *)arg, _IOC_SIZE(cmd));
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else if (_IOC_DIR(cmd) & _IOC_WRITE)
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err = !access_ok((void *) arg, _IOC_SIZE(cmd));
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err = !access_ok((void __user *)arg, _IOC_SIZE(cmd));
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if (err)
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return -EFAULT;
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@ -504,52 +504,52 @@ static long hantroenc_ioctl(struct file *filp,
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case _IOC_NR(HX280ENC_IOCGHWOFFSET): {
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u32 id;
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__get_user(id, (u32 *)arg);
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__get_user(id, (u32 __user *)arg);
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if (id >= total_core_num)
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return -EFAULT;
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__put_user(hantroenc_data[id].core_cfg.base_addr, (unsigned long *) arg);
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__put_user(hantroenc_data[id].core_cfg.base_addr, (u32 __user *)arg);
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break;
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}
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case _IOC_NR(HX280ENC_IOCGHWIOSIZE): {
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u32 id;
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u32 io_size;
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__get_user(id, (u32 *)arg);
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__get_user(id, (u32 __user *)arg);
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if (id >= total_core_num)
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return -EFAULT;
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io_size = hantroenc_data[id].core_cfg.iosize;
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__put_user(io_size, (u32 *) arg);
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__put_user(io_size, (u32 __user *)arg);
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return 0;
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}
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case _IOC_NR(HX280ENC_IOCGSRAMOFFSET):
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__put_user(sram_base, (unsigned long *) arg);
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__put_user(sram_base, (u32 __user *)arg);
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break;
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case _IOC_NR(HX280ENC_IOCGSRAMEIOSIZE):
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__put_user(sram_size, (unsigned int *) arg);
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__put_user(sram_size, (u32 __user *)arg);
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break;
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case _IOC_NR(HX280ENC_IOCG_CORE_NUM):
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__put_user(total_core_num, (unsigned int *) arg);
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__put_user(total_core_num, (u32 __user *)arg);
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break;
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case _IOC_NR(HX280ENC_IOCH_ENC_RESERVE): {
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u32 core_info;
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int ret;
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PDEBUG("Reserve ENC Cores\n");
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__get_user(core_info, (u32 *)arg);
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__get_user(core_info, (u32 __user *)arg);
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ret = ReserveEncoder(hantroenc_data, &core_info, filp);
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if (ret == 0)
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__put_user(core_info, (u32 *) arg);
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__put_user(core_info, (u32 __user *)arg);
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return ret;
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}
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case _IOC_NR(HX280ENC_IOCH_ENC_RELEASE): {
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u32 core_info;
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__get_user(core_info, (u32 *)arg);
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__get_user(core_info, (u32 __user *)arg);
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PDEBUG("Release ENC Core\n");
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@ -561,7 +561,7 @@ static long hantroenc_ioctl(struct file *filp,
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u32 core_id;
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u32 reg_value;
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__get_user(core_id, (u32 *)arg);
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__get_user(core_id, (u32 __user *)arg);
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PDEBUG("Enable ENC Core\n");
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if (hantroenc_data[core_id].is_reserved == 0)
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@ -576,9 +576,9 @@ static long hantroenc_ioctl(struct file *filp,
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if (down_interruptible(&hantroenc_data[core_id].core_suspend_sem))
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return -ERESTARTSYS;
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reg_value = (u32)ioread32((void *)(hantroenc_data[core_id].hwregs + 0x14));
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reg_value = (u32)ioread32(hantroenc_data[core_id].hwregs + 0x14);
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reg_value |= 0x01;
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iowrite32(reg_value, (void *)(hantroenc_data[core_id].hwregs + 0x14));
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iowrite32(reg_value, hantroenc_data[core_id].hwregs + 0x14);
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break;
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}
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@ -589,7 +589,7 @@ static long hantroenc_ioctl(struct file *filp,
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u32 i;
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u8 core_mapping;
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__get_user(core_info, (u32 *)arg);
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__get_user(core_info, (u32 __user *)arg);
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i = 0;
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core_mapping = (u8)(core_info&0xFF);
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@ -607,10 +607,10 @@ static long hantroenc_ioctl(struct file *filp,
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}
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err = WaitEncReady(hantroenc_data, &core_info, &irq_status);
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if (err == 0) {
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__put_user(irq_status, (unsigned int *)arg);
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__put_user(irq_status, (u32 __user *)arg);
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return core_info;//return core_id
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} else {
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__put_user(0, (unsigned int *)arg);
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__put_user(0, (u32 __user *)arg);
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return -1;
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}
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@ -619,7 +619,7 @@ static long hantroenc_ioctl(struct file *filp,
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case _IOC_NR(HX280ENC_IOC_WRITE_REGS): {
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struct enc_regs_buffer regs;
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err = copy_from_user(®s, (void *)arg, sizeof(regs));
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err = copy_from_user(®s, (void __user *)arg, sizeof(regs));
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if (err)
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return err;
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@ -631,7 +631,7 @@ static long hantroenc_ioctl(struct file *filp,
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case _IOC_NR(HX280ENC_IOC_READ_REGS): {
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struct enc_regs_buffer regs;
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err = copy_from_user(®s, (void *)arg, sizeof(regs));
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err = copy_from_user(®s, (void __user *)arg, sizeof(regs));
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if (err)
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return err;
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@ -814,7 +814,7 @@ static int hantro_enc_suspend(struct device *dev, pm_message_t state)
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if (hantroenc_data[i].irq_status & 0x04) {
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reg_buf = hantroenc_data[i].reg_buf;
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for (j = 0; j < hantroenc_data[i].core_cfg.iosize; j += 4)
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reg_buf[j/4] = ioread32((void *)(hantroenc_data[i].hwregs + j));
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reg_buf[j / 4] = ioread32(hantroenc_data[i].hwregs + j);
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}
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up(&hantroenc_data[i].core_suspend_sem);
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@ -838,7 +838,7 @@ static int hantro_enc_resume(struct device *dev)
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if (hantroenc_data[i].irq_status & 0x04) {
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for (j = 0; j < hantroenc_data[i].core_cfg.iosize; j += 4)
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iowrite32(reg_buf[j/4], (void *)(hantroenc_data[i].hwregs + j));
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iowrite32(reg_buf[j / 4], hantroenc_data[i].hwregs + j);
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hantroenc_data[i].reg_corrupt = 0;
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}
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}
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@ -1001,9 +1001,8 @@ static int ReserveIO(void)
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continue;
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}
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hantroenc_data[i].hwregs =
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(volatile u8 *) ioremap(hantroenc_data[i].core_cfg.base_addr,
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hantroenc_data[i].core_cfg.iosize);
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hantroenc_data[i].hwregs = ioremap(hantroenc_data[i].core_cfg.base_addr,
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hantroenc_data[i].core_cfg.iosize);
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if (hantroenc_data[i].hwregs == NULL) {
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pr_err("hantroenc: failed to ioremap HW regs\n");
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@ -1012,7 +1011,7 @@ static int ReserveIO(void)
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}
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/*read hwid and check validness and store it*/
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hwid = (u32)ioread32((void *)hantroenc_data[i].hwregs);
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hwid = (u32)ioread32(hantroenc_data[i].hwregs);
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PDEBUG("hwid=0x%08x\n", hwid);
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/* check for encoder HW ID */
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@ -1052,7 +1051,7 @@ static void ReleaseIO(void)
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//if (hantroenc_data[i].is_valid == 0)
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// continue;
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if (hantroenc_data[i].hwregs)
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iounmap((void *) hantroenc_data[i].hwregs);
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iounmap(hantroenc_data[i].hwregs);
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release_mem_region(hantroenc_data[i].core_cfg.base_addr, hantroenc_data[i].core_cfg.iosize);
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}
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}
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@ -1076,7 +1075,7 @@ static irqreturn_t hantroenc_isr(int irq, void *dev_id)
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u32 wClr;
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pr_err("hantroenc_isr:received IRQ but core is not reserved!\n");
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irq_status = (u32)ioread32((void *)(dev->hwregs + 0x04));
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irq_status = (u32)ioread32(dev->hwregs + 0x04);
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if (irq_status & 0x01) {
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/* Disable HW when buffer over-flow happen
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* HW behavior changed in over-flow
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@ -1084,20 +1083,20 @@ static irqreturn_t hantroenc_isr(int irq, void *dev_id)
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* new version: ask SW cleanup HWIF_ENC_E when buffer over-flow
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*/
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if (irq_status & 0x20)
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iowrite32(0, (void *)(dev->hwregs + 0x14));
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iowrite32(0, dev->hwregs + 0x14);
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/* clear all IRQ bits. (hwId >= 0x80006100) means IRQ is cleared by writting 1 */
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hwId = ioread32((void *)dev->hwregs);
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hwId = ioread32(dev->hwregs);
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majorId = (hwId & 0x0000FF00) >> 8;
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wClr = (majorId >= 0x61) ? irq_status : (irq_status & (~0x1FD));
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iowrite32(wClr, (void *)(dev->hwregs + 0x04));
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iowrite32(wClr, dev->hwregs + 0x04);
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}
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spin_unlock_irqrestore(&owner_lock, flags);
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return IRQ_HANDLED;
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}
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spin_unlock_irqrestore(&owner_lock, flags);
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irq_status = (u32)ioread32((void *)(dev->hwregs + 0x04));
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irq_status = (u32)ioread32(dev->hwregs + 0x04);
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if (irq_status & 0x01) {
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u32 hwId;
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u32 majorId;
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@ -1108,13 +1107,13 @@ static irqreturn_t hantroenc_isr(int irq, void *dev_id)
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* new version: ask SW cleanup HWIF_ENC_E when buffer over-flow
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*/
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if (irq_status & 0x20)
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iowrite32(0, (void *)(dev->hwregs + 0x14));
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iowrite32(0, dev->hwregs + 0x14);
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/* clear all IRQ bits. (hwId >= 0x80006100) means IRQ is cleared by writting 1 */
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hwId = ioread32((void *)dev->hwregs);
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hwId = ioread32(dev->hwregs);
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majorId = (hwId & 0x0000FF00) >> 8;
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wClr = (majorId >= 0x61) ? irq_status : (irq_status & (~0x1FD));
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iowrite32(wClr, (void *)(dev->hwregs + 0x04));
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iowrite32(wClr, dev->hwregs + 0x04);
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spin_lock_irqsave(&owner_lock, flags);
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dev->irq_received = 1;
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@ -1140,9 +1139,9 @@ static void ResetAsic(hantroenc_t *dev)
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for (n = 0; n < total_core_num; n++) {
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if (dev[n].is_valid == 0)
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continue;
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iowrite32(0, (void *)(dev[n].hwregs + 0x14));
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iowrite32(0, dev[n].hwregs + 0x14);
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for (i = 4; i < dev[n].core_cfg.iosize; i += 4)
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iowrite32(0, (void *)(dev[n].hwregs + i));
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iowrite32(0, dev[n].hwregs + i);
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}
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}
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