Function dpu_sc_misc_set_kachunk_cnt() is only used in
dpu-sc-misc.c, so staticize it to avoid build warning:
drivers/gpu/imx/dpu/dpu-sc-misc.c:72:5: warning: no previous prototype for ‘dpu_sc_misc_set_kachunk_cnt’ [-Wmissing-prototypes]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
The stress test is blocked in dma_fence_default_wait and missing
dpu_be_fence signaling leads to weston hang.
The root cause is unreasonable calling sequence of irq_handler and
atomic_inc.
We use refcnt in dpu_be_fence to sync dual dpu on 8QM. To avoid this
issue, we set refcnt = dpu_num when get_fence. Then each dpu blitter
will decrease the refcnt in irq_handler when doing sync and finally
signal the fence.
The same issue with LF-11223.
[ 1212.771073] sysrq: Show Blocked State
[ 1212.774848] task:kworker/u12:36 state stack:0 pid:975 tgid:975 ppid:2 flags:0x00000208
[ 1212.784142] Workqueue: events_unbound commit_work
[ 1212.788846] Call trace:
[ 1212.791282] __switch_to+0xe4/0x128
[ 1212.794765] __schedule+0x2d0/0x83c
[ 1212.798249] schedule+0x34/0xc8
[ 1212.801386] schedule_timeout+0xfc/0x108
[ 1212.805304] dma_fence_default_wait+0x1b8/0x1ec
[ 1212.809828] dma_fence_wait_timeout+0x84/0xa4
[ 1212.814178] drm_atomic_helper_wait_for_fences+0x174/0x234
[ 1212.819656] commit_tail+0x38/0x18c
[ 1212.823131] commit_work+0x14/0x20
[ 1212.826519] process_one_work+0x138/0x248
[ 1212.830524] worker_thread+0x320/0x438
[ 1212.834268] kthread+0x110/0x114
[ 1212.837492] ret_from_fork+0x10/0x20
Signed-off-by: Guangliu Ding <guangliu.ding@nxp.com>
Reviewed-by: Jiyu Yang <jiyu.yang@nxp.com>
Tested-by: Jared Hu <jared.hu@nxp.com>
Remove mode_valid function, video modes should be checked in
encoder or bridge drivers.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
This patch fixes the following fallthrough build warnings:
drivers/gpu/imx/imx8_dprc.c: In function ‘dprc_configure’:
drivers/gpu/imx/imx8_dprc.c:513:7: warning: this statement may fall through [-Wimplicit-fallthrough=]
513 | val |= YUV_EN;
drivers/gpu/imx/imx8_dprc.c:515:2: note: here
515 | case DRM_FORMAT_RGB565:
| ^~~~
drivers/gpu/imx/imx8_dprc.c: In function ‘dprc_probe’:
drivers/gpu/imx/imx8_dprc.c:817:21: warning: this statement may fall through [-Wimplicit-fallthrough=]
817 | dprc->has_aux_prg = true;
| ~~~~~~~~~~~~~~~~~~^~~~~~
drivers/gpu/imx/imx8_dprc.c:819:2: note: here
819 | case IMX_SC_R_DC_0_BLIT0:
| ^~~~
by replacing the /* fall-through */ comment with fallthrough;
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
According to the latest DC ADD(DisplayControllerSubsystem_MX8_B0_v0.58),
the DPR burst length of GPU standard tile should be 256byte or 512byte
in case of underrun with 256byte.
Based on tests done by Android team, 256byte works without DC underrun
issue(tracked by errata "ERR050183: DC: 4Kp60 performance limitations")
on both i.MX8qm and i.MX8qxp, while with the underrun issue by using
the original 128byte burst length.
So, this patch uses 256byte burst length first for GPU standard tile
since there should be only improvement and no downgrade or regression
(subject to change to 512byte in case of underrun).
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Tested-by: Richard Liu <xuegang.liu@nxp.com>
This patch checks the return value of imx_sc_misc_set_control() called
in dprc_prg_sel_configure() and generates warning dmesg in case the
return value is nonzero. The check makes Coverity happy.
This fixes Coverity issue: CID 10836597.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
This patch checks the return value of imx_sc_misc_set_control() called
in dprc_dpu_gpr_configure() and generates warning dmesg in case the
return value is nonzero. The check makes Coverity happy.
This fixes Coverity issue: CID 10836598.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
Instead of getting scu ipc handle from time to time in helpers
of the driver, we can get it in ->probe() once and cache it in
struct dprc. Also, we should check the return value of
imx_scu_get_handle() to get the handle in case it returns error
code. This makes Coverity happy.
This fixes two Coverity issues: CID 9993376 & CID 9993377.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
This patch adds helper dprc_disable_repeat_en() so that callers
may disable DPRC repeat_en.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fast-forward imx8_dprc driver from imx_4.14.y.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Liu Ying: scfw call updates and other small tweaks for upgrade]
Since we now use the flags passed over from the dowstream bridges, we
can safely set de_invert to false for the 'fsl,imx8mp-lcdif2' compatible
platform data.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Fix plane settings including fb pixel format, address and pitch when
enabling crtc to avoid an initial corrupt frame.
Tested-by: Sandor Yu <Sandor.yu@nxp.com>
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
hdmimix specific clocks are managed by imx8mp-hdmi-blk-ctrl.
remove lcdif3 specific code for hdmi.
lcidf3 could reuse the driver of compatible = "fsl,imx8mp-lcdif1".
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Since the reset bits in blk-ctrl are controlled by blk-ctrl driver,
so drop the unneeded device_reset() function call from imx_lcdifv3_probe().
Also, the software reset clear operation is done in runtime PM callback
->imx_lcdifv3_resume(), so drop the same clear operation from
imx_lcdifv3_probe() as well.
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
As mentioned in dsiplay_timing.h, with DISPLAY_FLAGS_PIXDATA_NEGEDGE set,
drive data on neg. edge, which means sample data on pos. edge. Also,
with DISPLAY_FLAGS_PIXDATA_POSEDGE set, drive data on pos. edge, which
means sample data on neg. edge.
The INV_PXCK bit of LCDIFV3_CTRL register is described in RM as below:
Polarity change of Pixel Clock.
0b - Display samples data on the falling edge
1b - Display samples data on the rising edge
So, with DISPLAY_FLAGS_PIXDATA_NEGEDGE set, the INV_PXCK bit should be set,
while with DISPLAY_FLAGS_PIXDATA_POSEDGE set, the bit should be cleared.
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
As a temporary solution, we need to get the mediamix block control
regmap through the 'fsl,gpr' lcdif DT node property to control lcdif
QoS and cache in the lcdif driver to achieve better system performance
and lcdif memory access performance. In the future, we'll use proper
and generic APIs in the lcdif driver to do the control instead of
accessing the mediamix block control register by our own.
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds i.MX93 LCDIFv3 display controller support.
A compatible string for i.MX93 LCDIFv3 is added in the driver.
Also, check of_id->data before dereferencing it because it is
NULL for i.MX93 LCDIFv3.
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
After switching to use upstream blkctl driver which will do reset along
with the power domain on/off, there's no need for client drivers to
do extra blkctl resets anymore.
For backwards compatibility support, this patch makes the usage of
"resets" properties optional. Then the driver can support both the
legacy dts and new dts using upstream blkctl in the future.
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
With mediamix blk ctrl enabled, clk is handled by blk ctrl driver and
work as SW power domain to devices, so no need clk here.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
We use PIGEON mode to do horizontal cropping. According to SoC design
team, the htotal value set in the HSYNC_PERIOD field of VDCTRL2 register
should not be modified comparing to non-cropping mode.
This patch fixes the below patch:
MLK-19152-1 gpu: imx: lcdif: realize fb horizontal crop via Pigeon Mode
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds MPU interface(8080 mode) support in the LCDIF driver
so that LCDIF may send frames to the sec-dsim MIPI DSI controller embedded
in i.MX8mm/mn via that interface. From the MIPI DSI controller perspective,
the input interface is called S-i80(Synchronous i80 Interface).
The general idea is to leverage the self refresh(SR) helpers offered by the
DRM core to make the external display device enter self refresh mode and
hence disable LCDIF when appropriate. The relevant DRM connectors'
conn_state->self_refresh_aware flags are inspected to determine whether to
use MPU interface or DOTCLK interface(also called RGB interface).
Since LCDIF will be disabled when the self refresh is active and the data
is transferred at modest rate, there are below known limitations:
1) The cur_frame_done interrupt comes at a lower frequency than the
display vsync signal frequency due to the low data transfer rate.
So, vblank events cannot reflect the real vsync pulses of the external
display.
2) Screen tearing phenomenon can be seen, because the frame update is
asynchronous to the external display self refresh and the LCDIF
controller does not support the 'Tearing Effect' mechanism.
3) The fbdev emulation and boot logo can not be updated onto screen in
time, because the external display often enters self refresh mode at
those stages. The boot logo will show up until the next time when
frame is sent to the external display via the MPU interface, e.g., when
the next framebuffer pan display operation is done after the logo is
ready in framebuffer. Like the below command line, writing to the
framebuffer sys node 'pan' frequently at background may make the
framebuffer emulation be a bit responsive.
while true; do echo 0,0 > /sys/class/graphics/fb0/pan; sleep 1; done &
Cc: Sandor Yu <Sandor.yu@nxp.com>
Cc: Wujian sun <wujian.sun_1@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Without axi clock, lcdif register access will cause system hang.
This issue happens when this driver built as module.
Signed-off-by: Jindong Yue <jindong.yue@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Add mode_valid() implementation for CRTC to filter out any
mode which cannot be supported by LCDIF. Only check the
CEA and DMT modes for pixel clock round rate is same with
the value from mode.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit d9be4b3d3b)
[ Liu Ying: Squash a build fix due to rebase upon v5.19-rc7 ]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add mode_valid() implementation for CRTC to filter out any
mode which cannot be supported by LCDIFv3. Only check the
CEA and DMT modes for pixel clock round rate is same with
the value from mode.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
[ Liu Ying: Squash a build fix due to rebase upon v5.19-rc7 ]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Moving LCDIF panic low/high threshold from code to dts to
set differnt value for differnt DDR type.
Signed-off-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit fa50cab5b6)
After 'resets' property has been added to lcdif1 node,
change to make use of this property for IP reset which
can be done by device_reset() simply.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Change LCDIFv3 burst size from 128B to 256B
to improve lpddr4 efficiency by adding about 200MB
Signed-off-by: Jian Li <jian.li@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit 10935dded7)
null return value check for of_id to reslove coverity ID 10058073.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
In imx_drm_suspend() and imx_drm_resume(), the display
pipeline will be disabled and enabled respectively, so
the correct suspend sequence should be master first to
disable the pipeline, and then the components can be
suspended, and resume sequence is obviously opposite.
So, to satisfy this sequence, use the late system sleep
PM ops to replace normal sleep PM ops for this purpose.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit fb41895e4f)
This is an issue reported by Coverity with CID 10020289. Since
the return ptr by of_match_device may be NULL, its dereference
should check the ptr value to avoid NULL ptr dereference issue.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
This is an issue reported by Coverity with CID 5433770. Since
the return ptr by of_match_device may be NULL, its dereference
should check the ptr value to avoid NULL ptr dereference issue.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
After the atomic plane update, the shadow load should be
enabled to make sure its update can take effect on next
frame in any cases. And this enable is better to be done
in CRTC's atomic_flush() which is called after plane's
atomic_update() is called.
Besides, the shadow load enable in controller enable is
unnecessary, so remove it.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
The current lcdifv3 common driver uses of_device_id data to determine
the data enable signal polarity of LCDIFv3. As required by LDB, the
polarity has to be "de_invert", so this patch introduces a compatible
string for LDB's LCDIFv3 and sets the "de_invert" flag to true in the
relevant of_device_id data.
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
There could be multiple LCDIFv3 instances in a SoC, so client
specific pdev id is needed. With this supported, LCDIFv3
instance1(for MIPI DSI) and instance2(for LDB) in i.MX8MP SoC
can add client pdev at the same time without id confliction
and thus can be both probed successfully.
As the i.MX8MP EVK bootloader can do splash screen with MIPI DSI,
we need properly reset LCDIFv3 instance1 in the LCDIFv3 driver,
otherwise, the LCDIFv3 instance2 cannot work(the reason behind
needs investigation). This also requires the two instances can
be probed at same time so that instance1 can be reset.
Reviewed-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
To support system suspend and resume, the system sleep
PM ops of suspend and resume are required to be added
for LCDIFv3 display.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
LCDIF DMA disable should be done before display is
turned off. And enough delay should be added after
DMA disable to make sure it is really done.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com>
Some display flicker issue may be observed when doing mode
switch or display disable and enable switch. The frame clear
bit can clear the FIFO data on every vsync blank period to
avoid any affect for next frame display and can solve this
kind of flicker issues.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Tested-by: Liu Ying <victor.liu@nxp.com>
The LCDIFv3 panic threshold enable register should be
'LCDIFV3_INT_ENABLE_D1' instead of 'LCDIFV3_PANIC0_THRES'.
So correct it.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
According to the LCDIFv3 specification, the input pixel
FIFO size is 8K(512 * 128bit) and the panic threshold
low and high should be chosen from 0 to 511, so correct
the thresholds calculation.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
The LCDIFv3 core driver is responsible to provide
controller registers configuration and create the
platform devices for the child port nodes. And the
platform devices later will attach to the related
DRM/KMS drivers via name match. And the LCDIFv3 is
completely different from the LCDIF controller
which is used on imx8mm and imx8mn platforms.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
[ Liu Ying: Remove drm_get_format_name() ]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
When built the driver as module, this typo error can
be found by compiler with below build error reported:
In file included from drivers/gpu/imx/lcdif/lcdif-common.c:20:
drivers/gpu/imx/lcdif/lcdif-common.c:78:25: error: ‘lcdif_dt_ids’ undeclared here (not in a function); did you mean ‘imx_lcdif_dt_ids’?
78 | MODULE_DEVICE_TABLE(of, lcdif_dt_ids);
| ^~~~~~~~~~~~
./include/linux/module.h:227:15: note: in definition of macro ‘MODULE_DEVICE_TABLE’
227 | extern typeof(name) __mod_##type##__##name##_device_table \
| ^~~~
./include/linux/module.h:227:21: error: ‘__mod_of__lcdif_dt_ids_device_table’ aliased to undefined symbol ‘lcdif_dt_ids’
227 | extern typeof(name) __mod_##type##__##name##_device_table \
| ^~~~~~
drivers/gpu/imx/lcdif/lcdif-common.c:78:1: note: in expansion of macro ‘MODULE_DEVICE_TABLE’
78 | MODULE_DEVICE_TABLE(of, lcdif_dt_ids);
| ^~~~~~~~~~~~~~~~~~~
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
