The for loop check condition should be "i < bc->onecell_data.num_domains".
Using "bc->onecell_data.num_domains" as condition is wrong, it will lead
to kernel panic.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
commit 52dd070c62 upstream.
With "quiet" set in bootargs, there is power domain failure:
"imx93_power_domain 44462400.power-domain: pd_off timeout: name:
44462400.power-domain, stat: 4"
The current power on opertation takes ISO state as power on finished
flag, but it is wrong. Before powering on operation really finishes,
powering off comes and powering off will never finish because the last
powering on still not finishes, so the following powering off actually
not trigger hardware state machine to run. SSAR is the last step when
powering on a domain, so need to wait SSAR done when powering on.
Since EdgeLock Enclave(ELE) handshake is involved in the flow, enlarge
the waiting time to 10ms for both on and off to avoid timeout.
Cc: stable@vger.kernel.org
Fixes: 0a0f7cc25d ("soc: imx: add i.MX93 SRC power domain driver")
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20240814124740.2778952-1-peng.fan@oss.nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
With "quite" set in bootargs, there is power domain failure:
"imx93_power_domain 44462400.power-domain: pd_off timeout: name:
44462400.power-domain, stat: 4"
The current power on opertation takes ISO state as power on finished
flag, but it is wrong. Need wait SSAR state when power on.
Since EdgeLock Enclave(ELE) handshake is involved in the flow, enlarge
the waiting time to 10ms for both on and off to avoid timeout.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
commit ddab91f4b2 upstream.
In the cases where the power domain connected to logics is allowed to
transition from a level(L)-->power collapse(0)-->retention(1) or
vice versa retention(1)-->power collapse(0)-->level(L) will cause the
logic to lose the configurations. The ARC does not support retention
to collapse transition on MxC rails.
The targets from SM8450 onwards the PLL logics of clock controllers are
connected to MxC rails and the recommended configurations are carried
out during the clock controller probes. The MxC transition as mentioned
above should be skipped to ensure the PLL settings are intact across
clock controller power on & off.
On older targets that do not split MX into MxA and MxC does not collapse
the logic and it is parked always at RETENTION, thus this issue is never
observed on those targets.
Cc: stable@vger.kernel.org # v5.17
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20240625-avoid_mxc_retention-v2-1-af9c2f549a5f@quicinc.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'v6.6.35' into lf-6.6.y
This is the 6.6.35 stable release
* tag 'v6.6.35': (268 commits)
Linux 6.6.35
zap_pid_ns_processes: clear TIF_NOTIFY_SIGNAL along with TIF_SIGPENDING
i2c: designware: Fix the functionality flags of the slave-only interface
...
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
commit 670c900f69 upstream.
When the dts file has multiple referrers to a single PD (e.g.
simple-framebuffer and dss nodes both point to the DSS power-domain) the
ti-sci driver will create two power domains, both with the same ID, and
that will cause problems as one of the power domains will hide the other
one.
Fix this checking if a PD with the ID has already been created, and only
create a PD for new IDs.
Fixes: efa5c01cd7 ("soc: ti: ti_sci_pm_domains: switch to use multiple genpds instead of one")
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20240415-ti-sci-pd-v1-1-a0e56b8ad897@ideasonboard.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'v6.6.34' into lf-6.6.y
This is the 6.6.34 stable release
* tag 'v6.6.34': (2530 commits)
Linux 6.6.34
smp: Provide 'setup_max_cpus' definition on UP too
selftests: net: more strict check in net_helper
...
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Conflicts:
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
drivers/net/ethernet/freescale/fec_ptp.c
drivers/pmdomain/imx/imx8mp-blk-ctrl.c
drivers/usb/dwc3/host.c
tools/perf/util/pmu.c
[ Upstream commit 697624ee8a ]
According to i.MX8MP RM and HDMI ADD, the fdcc clock is part of
hdmi rx verification IP that should not enable for HDMI TX.
But actually if the clock is disabled before HDMI/LCDIF probe,
LCDIF will not get pixel clock from HDMI PHY and print the error
logs:
[CRTC:39:crtc-2] vblank wait timed out
WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_atomic_helper.c:1634 drm_atomic_helper_wait_for_vblanks.part.0+0x23c/0x260
Add fdcc clock to LCDIF and HDMI TX power domains to fix the issue.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Link: https://lore.kernel.org/r/20240203165307.7806-5-aford173@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 5d7f58ee08 ]
devm_kasprintf() returns a pointer to dynamically allocated memory
which can be NULL upon failure. Ensure the allocation was successful
by checking the pointer validity.
Signed-off-by: Kunwu Chan <chentao@kylinos.cn>
Link: https://lore.kernel.org/r/20240118054257.200814-1-chentao@kylinos.cn
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit 883957bee5 ]
On SA8295P and SA8540P gfx.lvl is not provdied by rpmh, but rather is
handled by an external regulator (max20411). Drop gfx.lvl from the list
of power-domains exposed on this platform.
Fixes: f68f1cb343 ("soc: qcom: rpmhpd: add sc8280xp & sa8540p rpmh power-domains")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240125-sa8295p-gpu-v4-4-7011c2a63037@quicinc.com
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
commit 2a93c6cbd5 upstream.
Commit 'e3e56c050ab6 ("soc: qcom: rpmhpd: Make power_on actually enable
the domain")' aimed to make sure that a power-domain that is being
enabled without any particular performance-state requested will at least
turn the rail on, to avoid filling DeviceTree with otherwise unnecessary
required-opps properties.
But in the event that aggregation happens on a disabled power-domain, with
an enabled peer without performance-state, both the local and peer
corner are 0. The peer's enabled_corner is not considered, with the
result that the underlying (shared) resource is disabled.
One case where this can be observed is when the display stack keeps mmcx
enabled (but without a particular performance-state vote) in order to
access registers and sync_state happens in the rpmhpd driver. As mmcx_ao
is flushed the state of the peer (mmcx) is not considered and mmcx_ao
ends up turning off "mmcx.lvl" underneath mmcx. This has been observed
several times, but has been painted over in DeviceTree by adding an
explicit vote for the lowest non-disabled performance-state.
Fixes: e3e56c050a ("soc: qcom: rpmhpd: Make power_on actually enable the domain")
Reported-by: Johan Hovold <johan@kernel.org>
Closes: https://lore.kernel.org/linux-arm-msm/ZdMwZa98L23mu3u6@hovoldconsulting.com/
Cc: <stable@vger.kernel.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Tested-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20240226-rpmhpd-enable-corner-fix-v1-1-68c004cec48c@quicinc.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit f0e4a13564 upstream.
The power domain containing the Cortex-R7 CPU core on the R-Car V3H SoC
must always be in power-on state, unlike on other SoCs in the R-Car Gen3
family. See Table 9.4 "Power domains" in the R-Car Series, 3rd
Generation Hardware User’s Manual Rev.1.00 and later.
Fix this by marking the domain as a CPU domain without control
registers, so the driver will not touch it.
Fixes: 41d6d8bd8a ("soc: renesas: rcar-sysc: add R8A77980 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/fdad9a86132d53ecddf72b734dac406915c4edc0.1705076735.git.geert+renesas@glider.be
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit c41336f4d6 upstream.
If the power domains are registered first with genpd and *after that*
the driver attempts to power them on in the probe sequence, then it is
possible that a race condition occurs if genpd tries to power them on
in the same time.
The same is valid for powering them off before unregistering them
from genpd.
Attempt to fix race conditions by first removing the domains from genpd
and *after that* powering down domains.
Also first power up the domains and *after that* register them
to genpd.
Fixes: 59b644b01c ("soc: mediatek: Add MediaTek SCPSYS power domains")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20231225133615.78993-1-eugen.hristev@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This is the 6.6.3 stable release
* tag 'v6.6.3': (526 commits)
Linux 6.6.3
drm/amd/display: Change the DMCUB mailbox memory location from FB to inbox
drm/amd/display: Clear dpcd_sink_ext_caps if not set
...
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Conflicts:
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
drivers/usb/dwc3/core.c
commit 374de39d38 upstream.
Currently, The imx pgc power domain doesn't set the fwnode
pointer, which results in supply regulator device can't get
consumer imx pgc power domain device from fwnode when creating
a link.
This causes the driver core to instead try to create a link
between the parent gpc device of imx pgc power domain device and
supply regulator device. However, at this point, the gpc device
has already been bound, and the link creation will fail. So adding
the fwnode pointer to the imx pgc power domain device will fix
this issue.
Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com>
Tested-by: Emil Kronborg <emil.kronborg@protonmail.com>
Fixes: 3fb16866b5 ("driver core: fw_devlink: Make cycle detection more robust")
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20231020185949.537083-1-pengfei.li_1@nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit b131329b9b upstream.
Without this change, the NPU hangs when the 8th NN core is used.
It matches what the out-of-tree driver does.
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Fixes: 9a217b7e89 ("soc: amlogic: meson-pwrc: Add NNA power domain for A311D")
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20231016080205.41982-2-tomeu@tomeuvizoso.net
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 2e75396f1d upstream.
The commit c494a447c1 ("soc: bcm: bcm2835-power: Refactor ASB control")
refactored the ASB control by using a general function to handle both
the enable and disable. But this patch introduced a subtle regression:
we need to check if !!(readl(base + reg) & ASB_ACK) == enable, not just
check if (readl(base + reg) & ASB_ACK) == true.
Currently, this is causing an invalid register state in V3D when
unloading and loading the driver, because `bcm2835_asb_disable()` will
return -ETIMEDOUT and `bcm2835_asb_power_off()` will fail to disable the
ASB slave for V3D.
Fixes: c494a447c1 ("soc: bcm: bcm2835-power: Refactor ASB control")
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Stefan Wahren <stefan.wahren@i2se.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20231024101251.6357-2-mcanal@igalia.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* pm/next: (53 commits)
LF-10339-1 Revert "soc: imx: imx8m-blk-ctrl: set LCDIF panic read hurry level"
LF-9095: gpc: fwnode: Make imx pgc power domain also set the fwnode
LF-8359 soc: imx: imx93-blk-ctrl: fix power up domain fail during early noriq resume
LF-8093 pmdomain: imx: imx8mp-blk-ctrl: add missing HSIO noc setting
LF-9380-1: soc: imx8mp_blk: Add fdcc clock to hdmimix domain
...
Local tree uses a different solution which covers not only LCDIF.
So we have to revert upstream change.
This reverts commit 06a9a229b1.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Print a warning if resource not owned when trying to power it, instead
of returning an error that aborts the power sequence. This is required
for cockpit configuration.
Signed-off-by: Fabrice Goucem <fabrice.goucem@nxp.com>
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Currently, The imx pgc power domain doesn't set the fwnode
pointer, which results in supply regulator device can't get
consumer imx pgc power domain device from fwnode when creating
a link.
This causes the driver core to instead try to create a link
between the parent gpc device of imx pgc power domain device and
supply regulator device. However, at this point, the gpc device
has already been bound, and the link creation will fail. So adding
the fwnode pointer to the imx pgc power domain device will fix
this issue.
Signed-off-by: Pengfei Li <pengfei.li_1@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
After disabling PXP and having no displays connected, we met the following
suspend/resume hang issue on MX93 EVK board.
[ 407.272442] Enabling non-boot CPUs ...
[ 407.276514] Detected VIPT I-cache on CPU1
[ 407.276547] GICv3: CPU1: found redistributor 100 region 0:0x0000000048060000
[ 407.276587] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
[ 407.276940] CPU1 is up
[ 407.324202] imx93-blk-ctrl 4ac10000.system-controller: failed to power up domain: -13
[ 407.358945] imx93-blk-ctrl 4ac10000.system-controller: failed to power up domain: -13
[ 407.393678] imx93-blk-ctrl 4ac10000.system-controller: failed to power up domain: -13
...
The issue was introduced since the upstream commit
c24efa6732 ("PM: runtime: Capture device status before disabling runtime PM")
which will also check the power.last_status must be RPM_ACTIVE before
pm_runtime_get_sync() can return 1 (means already active) even pm_runtime
is disabled during no_irq resume stage.
However, the pm_runtime_set_active() we called ahead of
pm_runtime_get_sync() will not update power.last_status which probably like
a upstream kernel issue. But that's another issue which may worth an
extra fix.
This patch refers to the solution in the exist similar imx8m blkctrl driver [1]
that it will power up upstream domains during blkctl suspend first in
order to make sure the power.last_status to be RPM_ACTIVE. Then we can support
calling pm_runtime_get_sync in noirq resume stage.
After fixing, no need extra calling of pm_runtime_set_active() ahead anymore.
1. drivers/soc/imx/imx8m-blk-ctrl.c
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Adding the missing HSIO noc setting, the default NOC setting
of USB (NoC QoS generator mode is Bypass) cause the USB camera
test:
ml_nnstreamer_test.sh 2 2 -S G2D -d CPU
Generating the data buffer error:
[ 9980.403008] xhci-hcd xhci-hcd.1.auto: WARN: HC couldn't access mem fast enough for slot 1 ep 2
[ 9980.650211] xhci-hcd xhci-hcd.1.auto: WARN: HC couldn't access mem fast enough for slot 1 ep 2
[ 9980.662026] xhci-hcd xhci-hcd.1.auto: WARN: HC couldn't access mem fast enough for slot 1 ep 2
[ 9980.670719] xhci-hcd xhci-hcd.1.auto: Miss service interval error for slot 1 ep 2, set skip flag
[ 9980.670756] xhci-hcd xhci-hcd.1.auto: WARN: HC couldn't access mem fast enough for slot 1 ep 2
[ 9980.679381] xhci-hcd xhci-hcd.1.auto: Found td. Clear skip flag for slot 1 ep 2.
[ 9980.679413] xhci-hcd xhci-hcd.1.auto: ERROR Transfer event TRB DMA ptr not part of current TD ep_index 2 comp_code 1
[ 9980.689943] xhci-hcd xhci-hcd.1.auto: Looking for event-dma 00000000441c7e80 trb-start 00000000441c7e90 trb-end 00000000441c7e90 seg-start 00000000441c7000 seg-end 00000000441c7ff0
[ 9980.706752] xhci-hcd xhci-hcd.1.auto: overrun event on endpoint
[ 9980.708186] xhci-hcd xhci-hcd.1.auto: WARN: HC couldn't access mem fast enough for slot 1 ep 2
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
According to i.MX8MP RM and HDMI ADD, the fdcc clock is part of
hdmi rx verification IP that should not enable for HDMI TX.
But actually if the clock is disabled before HDMI/LCDIF probe,
LCDIF will not get pixel clock from HDMI PHY and print the error
logs:
[CRTC:39:crtc-2] vblank wait timed out
WARNING: CPU: 2 PID: 9 at drivers/gpu/drm/drm_atomic_helper.c:1634 drm_atomic_helper_wait_for_vblanks.part.0+0x23c/0x260
Add fdcc clock to LCDIF and HDMI TX power domains to fix the issue.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
For fused module, its pgc can't power up/down and clock is gated.
Because imx8m-blk-ctrl driver will pm_runtime_get_sync/pm_runtime_put
all power domains during suspend/resume. So we have to remove the
pgc and clock of fused module from blk-ctrl DTS node.
Update the driver to support such case.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
After remove the HDMIMIX reset & clock control from
the blk ctrl power off. The HDMI PHY power down control
and the HDMI CEC control still need to be put into blk
ctrl power off callback to make sure PHY should be power
down to save power and the CEC funtion disabled.
So add these two control back into power off callback.
Fixes: e0f67ca3a5 ("LF-8051 soc: imx: remove the reset/clock setting from the power off callback")
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
This patch is to fix the isp os08a20 4K mode capture and display
on 4k hdmi rarely has flicker.
Root cause: The dewarp noc data priority should decrease when use the 4k hdmi display.
The issue test command:
gst-launch-1.0 -v v4l2src device=/dev/video2 ! "video/x-raw,format=YUY2,width=3840,height=2160"
! queue ! waylandsink window-width=3840 window-height=2160 --no-position &
Signed-off-by: Alice Yuan <alice.yuan@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
Reviewed-by:Jian Li <lijian.li@nxp.com>
We should not do reset & clock gating before the ADB400 handshake done
when HDMIMIX power down. Change the flow to align with what we used
in ATF to fix the HDMI random hang issue due to ADB400 async bridge
power down failure.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
USB remote wakeup need its PHY on, so add USB PHY power domain
on active flag.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
To keep the real power domain(GPC) of USB PHY to be on, enable
the blk ctrl power domain dev to be wakeup capable, user need
enable it standard power interface of sys to make GPC keep its
power domain on.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
Per NXP ATF implementation, the HDMI flow would be:
Assert PD1 RESET_B to LOW -> MIX GPR
Function Clock ON -> MIX GPR
Power up HDMIX PD1 by GPC SW bit -> GPC SW bit set to 1’b1
Wait GPC SW bit self clear -> Polling GPC SW bit
Wait SRC Repair bit done -> Polling SRC SW bit, if repair done, the bit is asserted to 1’b1
Function Clock OFF -> MIX GPR
De-assert PD1 RESET_B to HIGH -> MIX GPR
Function Clock ON -> MIX GPR
Use udelay 20 for waiting SRC repair bit done. Use genpd notifier for
other steps
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Set hurry level for lcdif/isi/hdmi following NXP ATF implementation
to avoid video flick
Tested-by: Dong Aisheng <aisheng.dong@nxp.com>
Tested-by: Wujian sun <wujian.sun_1@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Accessing regmap will trigger system dump if the blk ctrl power domain
is down. There is no way to bind power domain to regmap for now,
so hide regmap from debugfs with NULL as dev pointer.
Reviewed-by: Aisheng Dong <aisheng.dong@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
During system suspend/resume, the blk ctrl power domain 'power_on' callback
may be called in noirq_resume context. As the device's runtime PM will be
disabled in 'late_suspend' stage, when system resume back, wehn calling
pm_runtime_get(_sync), it will return 'EACCES' error. To make sure
no error return, call 'pm_runtime_set_active' before pm_runtime_get(_sync)
to make sure blk ctrl device runtime PM is in active status.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Per errata:
ERR050531: VPU_NOC power down handshake may hang during VC8000E/VPUMIX
power up/down cycling.
Description: VC8000E reset de-assertion edge and AXI clock may have a
timing issue.
Workaround: Set bit2 (vc8000e_clk_en) of BLK_CLK_EN_CSR to 0 to gate off
both AXI clock and VC8000E clock sent to VC8000E and AXI clock sent to
VPU_NOC m_v_2 interface during VC8000E power up(VC8000E reset is
de-asserted by HW)
Need clear BIT2 of BLK_CLK_EN_CSR before power up VPU_H1, so
add a notifier with BIT2 cleared when GENPD_NOTIFY_PRE_ON and BIT2 set
when GENPD_NOTIFY_ON to match NXP downstream Arm Trusted Firmware
implementation.
NOTE: The downstream ATF has VPU_H1 CLK SET before do ADB400 HDSK, so follow
that procdure to avoid any suprise.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx8m blkctl does not support registers dumping with regmap debugfs
due to power domain required which is not supported by current regmap
core. So let's claim no debugfs support, otherwise the system may
hang when dumping registers through regmap debugfs.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Bind IMX8MP_HDMIBLK_PD_PAI together with IMX8MP_HDMIBLK_PD_PVI,
that PVI and PAI can power on or power off together, no need
extra steps to power on PAI.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Sandor Yu <sandor.yu@nxp.com>
The out of reset value of HSIO/HDMI NoC is not a valid value, we need
set it to a correct value. We only need to set it after power on.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The out of reset value of NoC is not a valid value, we need
set it to a correct value. We only need to set it after power on.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The NoC reset value for GPU, MLMIX and AUDIOMIX is not valid, need to set
it to a valid value after power up.
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
