After adding the dynamic setting for oclk-prsc, we no longer need to
set the static oclk-prsc method through DTS.
So drop it.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Before this, the default value of oclk_prsc is 2, or set by dts.
It cannot dynamically meet the provided cycle and pulse width
that are too large or too small by the user.
The current logic will try to set the duty cycle of the output pulse
to 50%.
However, due to IP restrictions, when priv->clk_freq is 333MHz, the
maximum high level time of the pulse is ~6ms. When the user sets a
period longer than 12ms, it cannot guarantee a 50% duty cycle.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Previously, when suspending, the PTP clock would be re-registered,
requiring the phc_index to be deinitialized.
After removing redundant PTP clock registrations, this deinitialization
was forgot to removed, causing the PTP to fail as a slave after resume.
So, remove the wrong deinitialization code.
Fixes: 438c5e9014 ("LF-11880-2 net: enetc: Add power off suspend/resume and WOL supports")
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
The NETC timer uses the NETC system clock as its clock source and
the rate is 333333333 Hz, so the clock period is about 3.000000003
ns. However, the NETC RM simplifies the clock frequency to 333MHz.
According to this value, the clock period is about 3.003003003 ns.
Therefore, the recommended fractional part of the period in NETC RM
is 0xc4ce07. And we also set this recommended value in the driver
based on NETC RM. But there is an issue when ENETC is used as the
master clock to synchronize the clock with FEC, it will cause the
clock offset to be a bit big, is about ±200ns and cannot converge
to ±100ns, because the accumulated value of the ENETC clock counter
is larger than the actual time. So we need to set the fractional
part of the period correctly.
In addition, the max_adj was set to 1000000 (in parts per billion)
before, so the max adjustable offset of the period is about ±0.003
ns. If the NETC timer still runs faster than the peer (master clock)
after adjusting the max offset of the period, PTP synchronization
will not be completed because the period cannot be shortened anymore.
Therefore, adjust the max_adj to increase the max adjustable offset
of the period.
Fixes: 9eb53327f2 ("LF-10640-6 ptp: add NETC PTP driver support for i.MX95")
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
In previous implementations, NETCMIX does not power off during suspend.
If NETCMIX powers off, all NETCMIX devices need to be reinitialized in the
resume process.
So, add this function support.
Support Wake-on-LAN functionality in suspend at the same time.
Need to execute the following command to set it as WOL mode.
# ethtool -s ethX wol g
When using WOL mode, NETCMIX will not power off during suspend.
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
The current driver does not support to handle TMR_TEVENT_ETS1EN event,
So remove the draft code for this event, otherwise, it causes Coverity
issue of uninitialized scalar variable.
Fixes: 9eb53327f2 ("LF-10640-6 ptp: add NETC PTP driver support for i.MX95")
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Remove unused member ierb_pdev of netc_timer, and this patch also
solves the compile warning of ptp_netc driver.
../drivers/ptp/ptp_netc.c:654:20: warning: variable 'ierb_pdev' is uninitialized when used here [-Wuninitialized]
priv->ierb_pdev = ierb_pdev;
^~~~~~~~~
../drivers/ptp/ptp_netc.c:618:35: note: initialize the variable 'ierb_pdev' to silence this warning
struct platform_device *ierb_pdev;
^
= NULL
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The i.MX95 NETC's Timer is different from the LS1028A NETC's Timer. In
addition to swapping the offsets of the upper 32-bit register and the
lower 32-bit register and adding ALRAM and FIPER control registers,
there are some main registers (such as the TMR_CTRL and TMR_ADD) that
are used in different ways even though they have the same functionality.
Yes, we can reuse the PTP driver of LS1028A and make some modifications
to support i.MX95 NETC's Timer, but this will undoubtedly increase the
complexity of the code and make the driver difficult to maintain. So we
have added a new driver named ptp_netc to support NETC Timer of i.MX95
and future i.MX SoCs such as i.MX943, i.MX952, etc.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Acked-by: Clark Wang <xiaoning.wang@nxp.com>
