commit c4fb7d2eac upstream.
The PMIC GLINK altmode driver currently supports at most two ports.
Fix the incomplete port sanity check on notifications to avoid
accessing and corrupting memory beyond the port array if we ever get a
notification for an unsupported port.
Fixes: 080b4e2485 ("soc: qcom: pmic_glink: Introduce altmode support")
Cc: stable@vger.kernel.org # 6.3
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231109093100.19971-1-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit eed6e57e9f ]
Commit c14e64b469 ("soc: qcom: llcc: Support chipsets that can
write to llcc") add the support for chipset where capacity based
allocation and retention through power collapse can be programmed
based on content of SCT table mentioned in the llcc driver where
the target like sdm845 where the entire programming related to it
is controlled in firmware. However, the commit introduces a bug
where capacity/retention register get overwritten each time it
gets programmed for each slice and that results in misconfiguration
of the register based on SCT table and that is not expected
behaviour instead it should be read modify write to retain the
configuration of other slices.
This issue is totally caught from code review and programming test
and not through any power/perf numbers so, it is not known what
impact this could make if we don't have this change however,
this feature are for these targets and they should have been
programmed accordingly as per their configuration mentioned in
SCT table like others bits information.
This change brings one difference where it keeps capacity/retention
bits of the slices that are not mentioned in SCT table in unknown
state where as earlier it was initialized to zero.
Fixes: c14e64b469 ("soc: qcom: llcc: Support chipsets that can write to llcc")
Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com>
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/1701876771-10695-1-git-send-email-quic_mojha@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This is the 6.6.3 stable release
* tag 'v6.6.3': (526 commits)
Linux 6.6.3
drm/amd/display: Change the DMCUB mailbox memory location from FB to inbox
drm/amd/display: Clear dpcd_sink_ext_caps if not set
...
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Conflicts:
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
drivers/usb/dwc3/core.c
This is the 6.6.2 stable release
* tag 'v6.6.2': (634 commits)
Linux 6.6.2
btrfs: make found_logical_ret parameter mandatory for function queue_scrub_stripe()
btrfs: use u64 for buffer sizes in the tree search ioctls
...
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Conflicts:
drivers/clk/imx/clk-imx8mq.c
drivers/clk/imx/clk-imx8qxp.c
drivers/media/i2c/ov5640.c
drivers/misc/pci_endpoint_test.c
[ Upstream commit 5692aeea5b ]
The device_for_each_child_node loop should call fwnode_handle_put()
before return in the error cases, to avoid resource leaks.
Let's fix this bug in pmic_glink_altmode_probe().
Signed-off-by: Lu Hongfei <luhongfei@vivo.com>
Link: https://lore.kernel.org/r/20230612133452.47315-1-luhongfei@vivo.com
[bjorn: Rebased patch, moved fw_handle_put() from jump target into the loop]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
* pm/next: (53 commits)
LF-10339-1 Revert "soc: imx: imx8m-blk-ctrl: set LCDIF panic read hurry level"
LF-9095: gpc: fwnode: Make imx pgc power domain also set the fwnode
LF-8359 soc: imx: imx93-blk-ctrl: fix power up domain fail during early noriq resume
LF-8093 pmdomain: imx: imx8mp-blk-ctrl: add missing HSIO noc setting
LF-9380-1: soc: imx8mp_blk: Add fdcc clock to hdmimix domain
...
* net/next: (344 commits)
LF-10639-5 net: enetc: Add xpcs support and set 10G support bits
LF-10639-4 net: pcs: xpcs: add mx95 serdes support
LF-10640-6 ptp: add NETC PTP driver support for i.MX95
LF-10639-3 net: phy: aquantia: enable LEDs to show the link state
LF-10639-1 enetc: mdio: add regulator support for both imdio and emdio bus
...
* origin/net/dpaa2: (44 commits)
bus: fsl-mc: fix double-free on mc_dev
dpaa2-switch: say that the bond device is offloaded as a bridge port
dpaa2-switch: cleanup the egress flood of an unused FDB
dpaa2-switch: offload port objects on the BOND interface
dpaa2-switch: add support for offloading upper bond devices
...
[ Upstream commit f86955f2b1 ]
As it was pointed out by Simon Ser, the DRM_MODE_CONNECTOR_USB connector
is reserved for the GUD devices. Other drivers (i915, amdgpu) use
DRM_MODE_CONNECTOR_DisplayPort even if the DP stream is handled by the
USB-C altmode. While we are still working on implementing the proper way
to let userspace know that the DP is wrapped into USB-C, change
connector type to be DRM_MODE_CONNECTOR_DisplayPort.
Fixes: 080b4e2485 ("soc: qcom: pmic_glink: Introduce altmode support")
Cc: Simon Ser <contact@emersion.fr>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Simon Ser <contact@emersion.fr>
Link: https://lore.kernel.org/r/20231010225229.77027-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
[ Upstream commit f1a1bc8775 ]
Usually there is only one llcc device. But if there were a second, even
a failed probe call would modify the global drv_data pointer. So check
if drv_data is valid before overwriting it.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Fixes: a3134fb09e ("drivers: soc: Add LLCC driver")
Link: https://lore.kernel.org/r/20230926083229.2073890-1-u.kleine-koenig@pengutronix.de
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
For i.MX9 family, the ANAMIX SoC ID register may not be
accessible from linux side on all the platforms. using
SiP call to get the soc info is more feasible way to
handle chip difference.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
It seems that there are circumstances when access to QBMAN through the
software portals will be delayed. Accessing some lower speeds interfaces
while also QBMAN commands are issued from the kernel will lead to
software timeouts happening in the dpaa2-eth driver.
What we have observed is that management commands like re-arming the
interrupts on a specific channel, waiting for a dequeue response to be
available etc, will take a longer time to complete.
All these commands have to wait for a valid bit to be set for the
command to be interpreted as successfully completed.
Increase the maximum number of times the Linux kernel drivers will busy
poll for a successful result of one of these commands.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
When running as a guest, under KVM, the CENA region is mapped
as device memory, so uncacheable. When the memory is mapped
as device memory, the unaligned accesses are not allowed.
Memcpy is optimized to transfer 8 bytes at a time regardless
of the start address and might cause alignment issues.
Signed-off-by: Diana Craciun <diana.craciun@nxp.com>
Setting the software portal configuration DE(dequeue stashing
enable) bit. This should enable the ACP (Accelerator Coherency
Port).
During test this improved performance on the LS2088a slightly. No
effect on the LX2160a.
Signed-off-by: Youri Querry <youri.querry_1@nxp.com>
Order preservation is a feature that will be supported
in dpni, dpseci and dpci devices.
This is a preliminary patch for the changes to be
introduced in the corresponding drivers.
Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Once we enable the cacheable portal memory, we need to do
cache flush for enqueue, vdq, buffer release, and management
commands, as well as invalidate and prefetch for the valid bit
of management command response and next index of dqrr.
Signed-off-by: Haiying Wang <Haiying.Wang@nxp.com>
Change cache enabled regsiter accessed to be cacheable
plus non-shareable to meet the performance requirement.
QMan's CENA region contains registers and structures that
are 64byte in size and are inteneded to be accessed using a
single 64 byte bus transaction, therefore this portal
memory should be configured as cache-enabled. Also because
the write allocate stash transcations of QBMan should be
issued as cachable and non-coherent(non-sharable), we
need to configure this region to be non-shareable.
Signed-off-by: Haiying Wang <Haiying.Wang@nxp.com>
Set up reserved memory regions for the QBMan devices under ACPI using
Contiguous Memory Allocations (CMA) at probe. Changing the following
default CMA kernel configs is required at build:
(a) Set CONFIG_CMA_SIZE_MBYTES to 256
(b) Set CONFIG_CMA_ALIGNMENT to 12
The qbman_init_private_mem() API is updated to indicate which device is
calling it (BMan or QMan).
Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
[Leo: move prop declaration into judgement block like upstream]
Signed-off-by: Li Yang <leoyang.li@nxp.com>
Add ACPI support for the Queue Manager Portal driver so that
it can be probed in both DT and ACPI cases.
Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Add ACPI support for the Queue Manager CCSR driver so that
it can be probed in both DT and ACPI cases.
Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Add ACPI support for the Buffer Manager Portal driver so that
it can be probed in both DT and ACPI cases.
Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Add ACPI support for the Buffer Manager CCSR driver so that
it can be probed in both DT and ACPI cases.
Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Interpret the Egress traffic management internal memory ECC errors that
can be reported by the QMAN_EADR. While CEETM isn't enabled in the code
base at the time of this patch, all values returned by the register
should be interpreted for safety.
While here, correct the number of QMAN_EDATA bits used for ECC errors in
the WQ context internal memory.
Furthermore, fix the address mask for ECC errors in the SW portal ring
internal memory.
All values are aligned with the QBMan Reference Manual.
Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
Change iMX8ULP A35 CPU frequency to default 800Mhz for OD, 650Mhz for ND.
And can support some special parts with higher CPU frequency in OD.
Change NIC_AD to 452Mhz for OD, 328Mhz for ND
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
On i.MX8ULP, the ddr controller can NOT support the automatic
refresh rate adjustment based on the MR4 contents. Instead, the
DDR controller used on i.MX8ULP can generate interrupt if LP4 MR4
reports temperature change(MR4.TUF=1). User can adjust the refresh
rate in the irq handler when LP4 reports temperature change.
There is no other good place to hold the ISR based refresh rate
adjustment support, just put it into the imx8ulp lpm file.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
There's a potential A-B/B-A deadlock between Clock and PM domain
framework in current kernel. Accessing PD clocks in genpd->power_on()/
power_off() callback is unsafe as mentioned in the commit
2b31e22d5376 ("PM: domains: add pm domain clocks support").
This patch switches to use the in core GENPD_FLAG_PM_PD_CLK feature for
imx8mp only to avoid such possible deadlock issue.
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Add a simple userspace controlled interface to adjust
the DDR frequency based on the user needs to save power.
It can also be customized to add more control to adjust
clock like bus fabric or other peripherals.
if sys_dvfs_enabled is true, system level OD/ND mode can be switched,
otherwise, only do ddr frequency scaling just as before
usage:
1. put DDR into low frequency:
echo 1 > /sys/devices/platform/imx8ulp-lpm/enable
2. DDR exit from low frequency:
echo 0 > /sys/devices/platform/imx8ulp-lpm/enable
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
On i.MX8ULP, when APD side enters suspend, need to notify RTD side
to do lifecycle management, so add suspend/resume support for this
purpose.
We need to add virtual platform device to implement the suspend/resume
callback as the rpmsg device driver don't have the support for device
specific suspend/resume support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Add rpmsg life cycle support on i.MX8ULP for APD side low power mode
state coordination with M core by sending rpmsg to M4 core. Currently,
only need to send nofity to M core for reboot/poweroff case. APD side
need to send rpmsg to M core side to let it know that APD side will
enter 'DPD' HW mode or do reboot. For both cases, M core side need to
re-init the rpmsg service when APD out of reset.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Allow i.MX8M power domain driver to be loaded as module.
And set the default value of IMX8M_PM_DOMAINS as ARCH_MXC.
Signed-off-by: Jindong Yue <jindong.yue@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Symbol driver_deferred_probe_check_state is not exported
in kernel, blocking this pm driver built as module.
Using -EPROBE_DEFER to replace it.
Signed-off-by: Jindong Yue <jindong.yue@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Some power domain need to be runtime always on to keep
the peripherals's weekup ability, for such power domain,
add the 'GENPD_FLAG_RPM_ALWAYS_ON' flag.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Add the active wakeup flag if a power domain has such requirement.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit c545e706e4)
The i.MX8M family is a set of NXP product focus on delivering
the latest and greatest video and audio experience combining
state-of-the-art media-specific features with high-performance
processing while optimized for lowest power consumption.
i.MX8MQ, i.MX8MM, i.MX8MN, even the furture i.MX8MP are all
belong to this family. A GPC module is used to manage all the
PU power domain on/off. But the situation is that the number of
power domains & the power up sequence has significate difference
on those SoCs. Even on the same SoC. The power up sequence still
has big difference. It makes us hard to reuse the GPCv2 driver to
cover the whole i.MX8M family. Each time a new SoC is supported in
the mainline kernel, we need to modify the GPCv2 driver to support
it. We need to add or modify hundred lines of code in worst case.
It is a bad practice for the driver maintainability.
This driver add a more generic power domain driver that the actual
power on/off is done by TF-A code. the abstraction give us the
possibility that using one driver to cover the whole i.MX8M family
in kernel side.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
In the last stage of deep sleep, software will trigger a Finite
State Machine (FSM) to control the hardware procedure, such a
board isolation, killing PLLs, removing power, and so on.
When the system is waked up by an interrupt, the FSM controls
the hardware to complete the early resume procedure.
This patch configure the EPU FSM preparing for deep sleep.
Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
FPGA on LX2160AQDS/LX2160ARDB connected on I2C bus, so add qixis driver
which is basically an i2c client driver to control FPGA.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
i.MX91/P only support ND/LD mode, so do necessary changes to
support it.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Current idle strap value 256 seems too small to meet most of the
ddr access perforamce requirement like ML benchmark & high resolution
video playback, so enlarge the default idle count time to 32768 to
meet the high perforamnce case ddr latency requirement.
For power consumption, when the system is idle, set idle strap to
'32768' only introduces very small VDD_SOC power increase. It should
be acceptable considering basic function & performance impact.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
The value of Device ID for i.MX91P is the same as i.MX93, so use
compatible to distinguish them.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
When the value of OSCCA_FUSE_READ_DIS is 1, i.MX93 is not allowed to
access the OCOTP registers. So split i.MX93 SoC device support
from soc-imx8m.c. The first 4 words of bank 6, a total of 128 bits, are
OTP_UNIQ_ID of i.MX93.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Use '%u' to print the idle strap value to let user more
easier to interpret and understand it.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
When user want to get the current system drive mode, show
the current ddr frequency info too. So refine the code for
this purpose.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Update the mode switching flow to fix some corner case issue:
1) when system switching from LD mode ND mode, the voltage should
be increased before increase the clock frequency;
2) when switching to LD/SWFFC mode, NIC AXI clock should be reduded
after all the clocks have been slow down to fix a random hang issue.
more likely, the NIC AXI can only be slow down when A55 related clock
has been reduced.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Refine the system wide run mode flow to add the dynamic
ld mode switching support. usage example:
OD mode:
echo 0 > /sys/devices/platform/imx93-lpm/mode;
ND mode:
echo 1 > /sys/devices/platform/imx93-lpm/mode;
LD mode:
echo 2 > /sys/devices/platform/imx93-lpm/mode;
LD mode with DDR scaling by SWFFC:
echo 3 > /sys/devices/platform/imx93-lpm/mode;
when DDR highest frequency is 3733MTS & system is running at
OD mode, the auto clock gating will be enabled by default to
balance the power & performance. For other case, need to be
enabled by user explictly based on actual case.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Based on i.MX93 CCB#44, the ND mode voltage should be
updated from 0.8V to 0.85V.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Add the DDR and SoC run mode(OD/OD) dynamic power saving support
on i.MX93. This low power control module provides four interface
to control the system wide OD/ND mode swithcing with DDR frequency
scaling by HWFFC, DDR scaling down to a frequency < half of the full
speed, DDR auto clock gating enable & auto clock gating idl strap
to fine tuning the performance & power based on the user case.
the supported controls are exported through the sys interface:
sys/devices/platform/imx93-lpm/mode;
sys/devices/platform/imx93-lpm/swffc;
sys/devices/platform/imx93-lpm/auto_clk_gating;
sys/devices/platform/imx93-lpm/idle_delay;
a). 'mode' is used to switching the od/nd mode with DDR HWFFC;
b). 'swffc' is used for scaling the DDR frequency to a lower one
with system switched to ND mode;
c). 'auto_clk_gating' is used to enable the DDR auto clock gating.
d). 'idle_delay' is used for fine tuning the DDR auto clock gating
strap. a larger value means after the DDRC AXI idle for that
clock count, the DDRC will put the DRAM into self-refresh with
clock gated to save power.
example:
1. switch the system to ND mode:
echo nd > sys/devices/platform/imx93-lpm/mode;
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Adding i.MX93 SoC device register function providers revision,
serial_number and soc_id for other drivers to use.
NOTE: soc-imx9.c depends on imx-ocotp-fsb-s400.c, so add
"depends on NVMEM_IMX_OCOTP_FSB_S400" otherwise we may meet the issue
imx9_init_soc: probe of 47510000.efuse:imx93-soc failed with error -2"
which appears at a low probability because nvmem_add_cells_from_of()
sometimes has not registered nvmem cells when soc-imx9.c calls
nvmem_cell_read_u64().
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Modify config as tristate and add module license to support
building imx8m soc driver as module.
Signed-off-by: Jindong Yue <jindong.yue@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Add rpmsg life cycle support on i.MX8ULP for APD side low power mode
state coordination with M core by sending rpmsg to M4 core. Currently,
only need to send nofity to M core for reboot/poweroff case. APD side
need to send rpmsg to M core side to let it know that APD side will
enter 'DPD' HW mode or do reboot. For both cases, M core side need to
re-init the rpmsg service when APD out of reset.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Fix below section mismatch build warning:
WARNING: modpost: vmlinux.o(.text+0x6b20b8): Section mismatch in reference
from the function imx8_soc_info() to the function .init.text:imx8mq_noc_init()
The function imx8_soc_info() references
the function __init imx8mq_noc_init().
This is often because imx8_soc_info lacks a __init
annotation or the annotation of imx8mq_noc_init is wrong.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
The config for lcdif should be removed, and need to add vpu
qos setting by default. this patch is just to add back the
vpu qos config that is missed when resolving cherry-pick
conflict for patch:
3a3f54750294: MLK-19380 driver: soc: update the noc QoS setting on imx8mq
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Allow imx8m busfreq driver to be loaded as a module.
Do not select IMX8M_BUSFREQ by default after enable ARCH_MXC.
Signed-off-by: Jindong Yue <jindong.yue@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
update the noc QoS setting for CPU & VPU on i.MX8MQ.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Jian Li <jian.li@nxp.com>
(cherry picked from commit 45d2dcaecce6d83e5c4a7e9488c651a05b0f05ac)
Config NOC to limit bandwidth to 4GB for both VPU
and CPU to avoid lcdif flickering only when lcdif is enabled.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 8ab89ebeb94a423792bf588bdf2354c5960d8f13)
When configuring the kernel to not support iMX, eg:
- make defconfig
- make lsdk.config
- CONFIG_ARCH_MXC=n
The build fails:
aarch64-fsl-linux-ld: drivers/soc/imx/secvio/imx-secvio-sc.o:
in function `int_imx_secvio_sc_disable_irq':
linux-nxp/drivers/soc/imx/secvio/imx-secvio-sc.c:385:
undefined reference to `imx_scu_irq_group_enable'
aarch64-fsl-linux-ld: drivers/soc/imx/secvio/imx-secvio-sc.o:
in function `int_imx_secvio_sc_enable_irq':
linux-nxp/drivers/soc/imx/secvio/imx-secvio-sc.c:343:
undefined reference to `imx_scu_irq_group_enable'
Makefile:1173: recipe for target 'vmlinux' failed
It happens because secvio module requires imx-scu-irq disabled
with CONFIG_ARCH_MXC=n.
This patch modify the Kconfig for the module to add a dependency
on IMX_SCU symbol.
Fixes: 262bd66fafcb (SSI-87: soc: imx: secvio: Add support for SNVS secvio and tamper via SCFW)
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
When the nvmem subsystem is not initialised at boot, the probe
will fail and an error message will be displayed.
In this case the message should not be printed as the driver will
be probed later.
This patch checks the error code from nvmem before printing the
message.
It also fixes the cleaning path as the driver was not exiting
properly.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Reviewed-by: Iuliana Prodan <iuliana.prodan@nxp.com>
The driver register an IRQ handle to SCU for security
violation interrupt.
When an interruption is fired, the driver inform the user.
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
When DRAM PLL clock is changed in TF-A, the DRAM PLL clock rate needs
to be updated, previous implementation uses dram_pll_clk which is
clock gate and it will NOT trigger clock rate update, need to use PLL
type clock which has CLK_GET_RATE_NOCACHE flag set and will trigger
clock rate recalculation. Otherwise, when system enters low bus mode,
checking clock rate via "cat /sys/kernel/debug/clk/dram_core_clk/clk_rate"
will NOT return the latest dram core clk rate.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
On i.MX6QP, the soc_id exported to the /sys/devices/soc0/soc_id
should be 'i.MX6QP'.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
[ Aisheng: update changes to drivers/soc/imx/soc-imx.c ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
On i.MX8M SOC family, we can support LPDDR4, DDR4 or DDR3L, we may need
to support different setpoint for audio & low bus mode on different DDR type,
So update the code to get all the supported setpoint info from ATF.
The maximum setpoints that can be supported by hardware is 4, if the drate
for a setpoint is '0', that means this setpoint is not enabled. We can use
these info to find out the lowest drate setpoint for audio & low bus mode.
BuildInfo:
- ATF 59fe78cfe7
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
The 100MTS low bus mode can be only supported by i.MX8MQ Rev2.1 and
future TO. So necessary check is added to identify the chip revision
when doing busfreq mode switch.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Use soc_device_metch instead of global imx_get_soc_revision
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
This reverts commit 7560cff21b7b92127675d5e955874af2827a9bca.
drivers/soc/imx/busfreq-imx8mq.o: In function `reduce_bus_freq':
/home/b29396/Work/linux/dash-linux-devel/build_v8/../drivers/soc/imx/busfreq-imx8mq.c:193: undefined reference to `imx_get_soc_revision'
/home/b29396/Work/linux/dash-linux-devel/build_v8/../drivers/soc/imx/busfreq-imx8mq.c:120: undefined reference to `imx_get_soc_revision'
drivers/soc/imx/busfreq-imx8mq.o: In function `set_high_bus_freq':
/home/b29396/Work/linux/dash-linux-devel/build_v8/../drivers/soc/imx/busfreq-imx8mq.c:327: undefined reference to `imx_get_soc_revision'
/home/b29396/Work/linux/dash-linux-devel/Makefile:1052: recipe for target 'vmlinux' failed
make[1]: *** [vmlinux] Error 1
upstream kernel did not export imx_get_soc_revision for mx8.
Need find a better way to support for both mx8m and mx8.
This patch fixes coverity issue of "divide by 0".
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit ed044f6d78)
The 100MTS low bus mode can be only supported by i.MX8MQ Rev2.1 and
future TO. So necessary check is added to identify the chip revision
when doing busfreq mode switch.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit a906afb17d)
add busfreq support on i.MX8MM. when system is running at low bus or
audio bus mode, the dram & bus clock will be reduced to a lower rate:
NOC: 150MHZ, AXI: 24MHz, AXI 20MHZ, DRAM core clock: 25MHz.
when system is running at high bus mode, all the bus clock and dram
clock will be restore to the highest one.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 4984e653a6)
Currently, on imx8mq evk board, we only support 3200mts and 667mts
frequency setpoints. So the DDR DVFS flow need to be updated accordingly.
The dram pll and dram apb clock rate is changed in ATF when doing frequency,
in kernel side, we need to call the clk API to update the clock rate info
in clock tree.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit a69c3794f5)
A 'return' statement is missed before, So the mutex will be unlocked
twice, in some corner case, one core will unlock the mutex that locked
by anohter core wrongly. Then lead to concurrent access to the DVFS
at the same time.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit 659615af4d)
If the system is currently in low bus mode, if the audio device
request the audio bus mode, the NOC, AHB and AXI bus clock rate
will be set wrongly, then bus will run at very low frequency, then
lead to audio playback underrun.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Tested-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 3a2a988cc0)
reduce the NOC, main AXI and AHB bus clock frequency to save power when DDR enter low
frequency mode. VDDSOC is ~195mA during video play, and ~180mA in idle.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit e109b34d30)
If audio device is the only that access to ddr memory, the DDR
frequency can be reduce to 25MHz to save power. when DDR run in
25MHz frequency, the memory bandwidth is about 66MB/s, it can
meet the performance requirement for audio only case.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 7c2389b6dc)
Add busfreq driver support on i.MX8MQ. The busfreq driver is
mainly used for dynamic DDR frequency change for power saving
feature. When there is no peripheral or DMA device has direct
access to DDR memory, we can lower the DDR frequency to save
power. Currently, we support frequency setpoint for LPDDR4:
(1): 3200mts, the DDRC core clock is sourced from 800MHz
dram_pll, the DDRC apb clock is 200MHz.
(2): 400mts, the DDRC core clock is source from sys1_pll_400m,
the DDRC apb clock is is sourced from sys1_pll_40m.
(3): 100mts, the DDRC core clock is sourced from sys1_pll_100m,
the DDRC apb clock is sourced from sys1_pll_40m.
In our busfreq driver, we have three mode supported:
* high bus mode <-----> 3200mts;
* audio bus mode <-----> 400mts;
* low bus mode <-----> 100mts;
The actual DDR frequency is done in ARM trusted firmware by calling
the SMCC SiP service call.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Use CONFIG_IMX8M_BUSFREQ
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
[ Leo: Updated the confusing Kconfig description of HAVE_IMX_BUSFREQ ]
Signed-off-by: Li Yang <leoyang.li@nxp.com>
- Sort out a few Kconfig dependency issues for the rich set of RISC-V
non-coherent DMA support.
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Merge tag 'renesas-fixes-for-v6.6-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
Renesas fixes for v6.6 (take three)
- Sort out a few Kconfig dependency issues for the rich set of RISC-V
non-coherent DMA support.
* tag 'renesas-fixes-for-v6.6-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM
riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT
riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT
Link: https://lore.kernel.org/r/cover.1698312384.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ARCH_R9A07G043 has its own non-standard global pool based DMA coherent
allocator, which conflicts with the remap based RISCV_ISA_ZICBOM version.
Add a proper dependency.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231018052654.50074-4-hch@lst.de
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
AngeloGioacchino Del Regno is stepping in as co-maintainer for the
MediaTek SoC platform and starts by sending some dts fixes for
the mt8195 platform that had been pending for a while.
On the ixp4xx platform, Krzysztof Halasa steps down as co-maintainer,
reflecting that Linus Walleij has been handling this on his own
for the past few years.
Generic RISC-V kernels are now marked as incompatible with the
RZ/Five platform that requires custom hacks both for managing
its DMA bounce buffers and for addressing low virtual memory.
Finally, there is one bugfix for the AMDTEE firmware driver
to prevent a use-after-free bug.
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Merge tag 'soc-fixes-6.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC fixes from Arnd Bergmann:
"AngeloGioacchino Del Regno is stepping in as co-maintainer for the
MediaTek SoC platform and starts by sending some dts fixes for the
mt8195 platform that had been pending for a while.
On the ixp4xx platform, Krzysztof Halasa steps down as co-maintainer,
reflecting that Linus Walleij has been handling this on his own for
the past few years.
Generic RISC-V kernels are now marked as incompatible with the RZ/Five
platform that requires custom hacks both for managing its DMA bounce
buffers and for addressing low virtual memory.
Finally, there is one bugfix for the AMDTEE firmware driver to prevent
a use-after-free bug"
* tag 'soc-fixes-6.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
IXP4xx MAINTAINERS entries
arm64: dts: mediatek: mt8195: Set DSU PMU status to fail
arm64: dts: mediatek: fix t-phy unit name
arm64: dts: mediatek: mt8195-demo: update and reorder reserved memory regions
arm64: dts: mediatek: mt8195-demo: fix the memory size to 8GB
MAINTAINERS: Add Angelo as MediaTek SoC co-maintainer
soc: renesas: Make ARCH_R9A07G043 (riscv version) depend on NONPORTABLE
tee: amdtee: fix use-after-free vulnerability in amdtee_close_session
Randy reported a randconfig build issue against linux-next:
WARNING: unmet direct dependencies detected for ERRATA_ANDES
Depends on [n]: RISCV_ALTERNATIVE [=n] && RISCV_SBI [=y]
Selected by [y]:
- ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y] && NONPORTABLE [=y] && RISCV_SBI [=y]
../arch/riscv/errata/andes/errata.c:59:54: warning: 'struct alt_entry' declared inside parameter list will not be visible outside of this definition or declaration
59 | void __init_or_module andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
On RISC-V, alternatives are not usable in XIP kernels, which this
randconfig happened to select. Rather than add a check for whether
alternatives are available before selecting the ERRATA_ANDES config
option, rework the R9A07G043 Kconfig entry to depend on the
configuration options required to support its non-standard cache
coherency implementation.
Without these options enabled, the SoC is effectively non-functional to
begin with, so there's an extra benefit in preventing the creation of
non-functional kernels.
The "if RISCV_DMA_NONCOHERENT" can be dropped, as ERRATA_ANDES_CMO will
select it.
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Closes: https://lore.kernel.org/all/09a6b0f0-76a1-45e3-ab52-329c47393d1d@infradead.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231012-pouch-parkway-7d26c04b3300@spud
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Drew found "CONFIG_DMA_GLOBAL_POOL=y causes ADMA buffer alloc to fail"
the log looks like:
mmc0: Unable to allocate ADMA buffers - falling back to standard DMA
The logic is: generic riscv defconfig selects ARCH_RENESAS then
ARCH_R9A07G043 which selects DMA_GLOBAL_POOL, which assumes all
non-dma-coherent riscv platforms have a dma global pool, this assumption
seems not correct. And I believe DMA_GLOBAL_POOL should not be
selected by ARCH_SOCFAMILIY, instead, only ARCH under some specific
conditions can select it globaly, for example NOMMU ARM and so on,
because it's designed for special cases such as "nommu cases where
non-cacheable memory lives in a fixed place in the physical address
map" as pointed out by Robin.
Fix the issue by making ARCH_R9A07G043 (riscv version) depend on
NONPORTABLE, thus generic defconfig won't select ARCH_R9A07G043 by
default. And even for random config case, there will be less debug
effort once we see NONPORTABLE is enabled.
Reported-by: Drew Fustini <dfustini@baylibre.com>
Closes: https://lore.kernel.org/linux-riscv/ZRuamJuShOnvP1pr@x1/
Fixes: 484861e09f ("soc: renesas: Kconfig: Select the required configs for RZ/Five SoC")
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Drew Fustini <dfustini@baylibre.com>
Link: https://lore.kernel.org/r/20231004150856.2540-1-jszhang@kernel.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The syscon poweroff and reboot nodes logically belong to the Power
Management Unit so populate possible children.
Without it, the reboot/poweroff feature becomes unavailable.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Now, "loongson,ls2k0500-pmc" is used as fallback compatible, so the
ls2k1000 compatible in the driver can be dropped directly.
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Since commit 67694c076b ("soc: loongson2_pm: add power management
support"), the Loongson-2K PM driver was added, but it didn't update the
Kconfig entry for the INPUT dependency, leading to build errors, so
update the Kconfig entry to depend on INPUT.
/opt/crosstool/gcc-13.2.0-nolibc/loongarch64-linux/bin/loongarch64-linux-ld:
drivers/soc/loongson/loongson2_pm.o: in function `loongson2_power_button_init':
/work/lnx/next/linux-next-20230825/LOONG64/../drivers/soc/loongson/loongson2_pm.c:101:(.text+0x350): undefined reference to `input_allocate_device'
/opt/crosstool/gcc-13.2.0-nolibc/loongarch64-linux/bin/loongarch64-linux-ld:
/work/lnx/next/linux-next-20230825/LOONG64/../drivers/soc/loongson/loongson2_pm.c:109:(.text+0x3dc): undefined reference to `input_set_capability'
/opt/crosstool/gcc-13.2.0-nolibc/loongarch64-linux/bin/loongarch64-linux-ld:
/work/lnx/next/linux-next-20230825/LOONG64/../drivers/soc/loongson/loongson2_pm.c:111:(.text+0x3e4): undefined reference to `input_register_device'
/opt/crosstool/gcc-13.2.0-nolibc/loongarch64-linux/bin/loongarch64-linux-ld:
/work/lnx/next/linux-next-20230825/LOONG64/../drivers/soc/loongson/loongson2_pm.c:125:(.text+0x3fc): undefined reference to `input_free_device'
/opt/crosstool/gcc-13.2.0-nolibc/loongarch64-linux/bin/loongarch64-linux-ld: drivers/soc/loongson/loongson2_pm.o: in function `input_report_key':
/work/lnx/next/linux-next-20230825/LOONG64/../include/linux/input.h:425:(.text+0x58c): undefined reference to `input_event'
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Commit 836fb30949 ("soc: imx8m: Enable OCOTP clock before reading the
register") added configuration to enable the OCOTP clock before
attempting to read from the associated registers.
This same kexec issue is present with the imx8m SoCs that use the
imx8mm_soc_uid function (e.g. imx8mp). This requires the imx8mm_soc_uid
function to configure the OCOTP clock before accessing the associated
registers. This change implements the same clock enable functionality
that is present in the imx8mq_soc_revision function for the
imx8mm_soc_uid function.
Signed-off-by: Nathan Rossi <nathan.rossi@digi.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Fixes: 836fb30949 ("soc: imx8m: Enable OCOTP clock before reading the register")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Prabhakar <prabhakar.csengg@gmail.com> says:
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
non-coherent DMA support for AX45MP
====================================
On the Andes AX45MP core, cache coherency is a specification option so it
may not be supported. In this case DMA will fail. To get around with this
issue this patch series does the below:
1] Andes alternative ports is implemented as errata which checks if the
IOCP is missing and only then applies to CMO errata. One vendor specific
SBI EXT (ANDES_SBI_EXT_IOCP_SW_WORKAROUND) is implemented as part of
errata.
Below are the configs which Andes port provides (and are selected by
RZ/Five):
- ERRATA_ANDES
- ERRATA_ANDES_CMO
OpenSBI patch supporting ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI is now
part v1.3 release.
2] Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
block that allows dynamic adjustment of memory attributes in the runtime.
It contains a configurable amount of PMA entries implemented as CSR
registers to control the attributes of memory locations in interest.
OpenSBI configures the PMA regions as required and creates a reserve memory
node and propagates it to the higher boot stack.
Currently OpenSBI (upstream) configures the required PMA region and passes
this a shared DMA pool to Linux.
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pma_resv0@58000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x58000000 0x0 0x08000000>;
no-map;
linux,dma-default;
};
};
The above shared DMA pool gets appended to Linux DTB so the DMA memory
requests go through this region.
3] We provide callbacks to synchronize specific content between memory and
cache.
4] RZ/Five SoC selects the below configs
- AX45MP_L2_CACHE
- DMA_GLOBAL_POOL
- ERRATA_ANDES
- ERRATA_ANDES_CMO
----------x---------------------x--------------------x---------------x----
* b4-shazam-merge:
soc: renesas: Kconfig: Select the required configs for RZ/Five SoC
cache: Add L2 cache management for Andes AX45MP RISC-V core
dt-bindings: cache: andestech,ax45mp-cache: Add DT binding documentation for L2 cache controller
riscv: mm: dma-noncoherent: nonstandard cache operations support
riscv: errata: Add Andes alternative ports
riscv: asm: vendorid_list: Add Andes Technology to the vendors list
Link: https://lore.kernel.org/r/20230818135723.80612-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
changes to the clk framework this time around. That's probably because everyone
was on vacation (yours truly included). We did lose a couple clk drivers this
time around because nobody was using those devices. That skews the diffstat a
bit, but either way, nothing looks out of the ordinary here. The usual suspects
are chugging along adding support for more SoCs and fixing bugs.
If I had to choose, I'd say the theme for the past few months has been
"polish". There's quite a few patches that migrate to
devm_platform_ioremap_resource() in here. And there's more than a handful of
patches that move the NR_CLKS define from the DT binding header to the driver.
There's even patches that migrate drivers to use clk_parent_data and clk_hw to
describe clk tree topology. It seems that the spring (summer?) cleaning bug got
some folks, or the semiconductor shortage finally hit the software side.
New Drivers:
- StarFive JH7110 SoC clock drivers
- Qualcomm IPQ5018 Global Clock Controller driver
- Versa3 clk generator to support 48KHz playback/record with audio codec on
RZ/G2L SMARC EVK
Removed Drivers:
- Remove non-OF mmp clk drivers
- Remove OXNAS clk driver
Updates:
- Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc
- Move defines for numbers of clks (NR_CLKS) from DT headers to drivers
- Introduce kstrdup_and_replace() and use it
- Add PLL rates for Rockchip rk3568
- Add the display clock tree for Rockchip rv1126
- Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and RZ/G2 SoCs
- Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource()
- Fix function name in a comment in ccu_mmc_timing.c
- Parameter name correction for ccu_nkm_round_rate()
- Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e. consider alternative
parent rates when determining clock rates
- Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi
- Support finding closest (as opposed to closest but not higher) clock rate
for NM, NKM, mux and div type clocks, as use it for Allwinner A64 pll-video0
- Prefer current parent rate if able to generate ideal clock rate for Allwinner NKM clocks
- Clean up Qualcomm SMD RPM driver, with interconnect bus clocks moved out to
the interconnect drivers
- Fix various PM runtime bugs across many Qualcomm clk drivers
- Migrate Qualcomm MDM9615 is to parent_hw and parent_data
- Add network related resets on Qualcomm IPQ4019
- Add a couple missing USB related clocks to Qualcomm IPQ9574
- Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock controller
- In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs, and GPLL1 are
added, while PCIe pipe clock, SDCC rcg ops are corrected
- Add missing GDSCs to and correct GDSCs for the SC8280XP global clock controller driver
- Support retention for the Qualcomm SC8280XP display clock controller GDSCs.
- Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE to fix
issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250,
while sm8450 is corrected to use floor ops
- Correct Qualcomm SM6350 GPU clock controller's clock supplies
- Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver
- Add missing OXILICX GDSC to Qualcomm MSM8226 GCC
- Change the delay in the Qualcomm reset controller to fsleep() for correctness
- Extend the Qualcomm SM83550 Video clock controller to support SC8280XP
- Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3,
M3-W, and M3-N SoCs
- Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M
- Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five
- Add the PDM IPC clock for i.MX93
- Add 519.75MHz frequency support for i.MX9 PLL
- Simplify the .determine_rate() implementation for i.MX GPR mux
- Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource()
- Add the audio mux clock to i.MX8
- Fix the SPLL2 MULT range for PLLv4
- Update the SPLL2 type in i.MX8ULP
- Fix the SAI4 clock on i.MX8MP
- Add silicon revision print for i.MX25 on clocks init
- Drop the return value from __mx25_clocks_init()
- Fix the clock pauses on no-op set_rate for i.MX8M composite clock
- Drop restrictions for i.MX PLL14xx and fix its max prediv value
- Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to allow
glitch free switching
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk subsystem updates from Stephen Boyd:
"This pull request is full of clk driver changes. In fact, there aren't
any changes to the clk framework this time around. That's probably
because everyone was on vacation (yours truly included). We did lose a
couple clk drivers this time around because nobody was using those
devices. That skews the diffstat a bit, but either way, nothing looks
out of the ordinary here. The usual suspects are chugging along adding
support for more SoCs and fixing bugs.
If I had to choose, I'd say the theme for the past few months has been
"polish". There's quite a few patches that migrate to
devm_platform_ioremap_resource() in here. And there's more than a
handful of patches that move the NR_CLKS define from the DT binding
header to the driver. There's even patches that migrate drivers to use
clk_parent_data and clk_hw to describe clk tree topology. It seems
that the spring (summer?) cleaning bug got some folks, or the
semiconductor shortage finally hit the software side.
New Drivers:
- StarFive JH7110 SoC clock drivers
- Qualcomm IPQ5018 Global Clock Controller driver
- Versa3 clk generator to support 48KHz playback/record with audio
codec on RZ/G2L SMARC EVK
Removed Drivers:
- Remove non-OF mmp clk drivers
- Remove OXNAS clk driver
Updates:
- Add __counted_by to struct clk_hw_onecell_data and struct
spmi_pmic_div_clk_cc
- Move defines for numbers of clks (NR_CLKS) from DT headers to
drivers
- Introduce kstrdup_and_replace() and use it
- Add PLL rates for Rockchip rk3568
- Add the display clock tree for Rockchip rv1126
- Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and
RZ/G2 SoCs
- Convert sun9i-mmc clock to use
devm_platform_get_and_ioremap_resource()
- Fix function name in a comment in ccu_mmc_timing.c
- Parameter name correction for ccu_nkm_round_rate()
- Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e.
consider alternative parent rates when determining clock rates
- Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi
- Support finding closest (as opposed to closest but not higher)
clock rate for NM, NKM, mux and div type clocks, as use it for
Allwinner A64 pll-video0
- Prefer current parent rate if able to generate ideal clock rate for
Allwinner NKM clocks
- Clean up Qualcomm SMD RPM driver, with interconnect bus clocks
moved out to the interconnect drivers
- Fix various PM runtime bugs across many Qualcomm clk drivers
- Migrate Qualcomm MDM9615 is to parent_hw and parent_data
- Add network related resets on Qualcomm IPQ4019
- Add a couple missing USB related clocks to Qualcomm IPQ9574
- Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock
controller
- In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs,
and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are
corrected
- Add missing GDSCs to and correct GDSCs for the SC8280XP global
clock controller driver
- Support retention for the Qualcomm SC8280XP display clock
controller GDSCs.
- Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE
to fix issues with missing parent clocks across sc7180, sm7150,
sm6350 and sm8250, while sm8450 is corrected to use floor ops
- Correct Qualcomm SM6350 GPU clock controller's clock supplies
- Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver
- Add missing OXILICX GDSC to Qualcomm MSM8226 GCC
- Change the delay in the Qualcomm reset controller to fsleep() for
correctness
- Extend the Qualcomm SM83550 Video clock controller to support
SC8280XP
- Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and
R-Car H3, M3-W, and M3-N SoCs
- Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M
- Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five
- Add the PDM IPC clock for i.MX93
- Add 519.75MHz frequency support for i.MX9 PLL
- Simplify the .determine_rate() implementation for i.MX GPR mux
- Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource()
- Add the audio mux clock to i.MX8
- Fix the SPLL2 MULT range for PLLv4
- Update the SPLL2 type in i.MX8ULP
- Fix the SAI4 clock on i.MX8MP
- Add silicon revision print for i.MX25 on clocks init
- Drop the return value from __mx25_clocks_init()
- Fix the clock pauses on no-op set_rate for i.MX8M composite clock
- Drop restrictions for i.MX PLL14xx and fix its max prediv value
- Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to
allow glitch free switching"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (207 commits)
clk: qcom: Fix SM_GPUCC_8450 dependencies
clk: lmk04832: Support using PLL1_LD as SPI readback pin
clk: lmk04832: Don't disable vco clock on probe fail
clk: lmk04832: Set missing parent_names for output clocks
clk: mvebu: Convert to devm_platform_ioremap_resource()
clk: nuvoton: Convert to devm_platform_ioremap_resource()
clk: socfpga: agilex: Convert to devm_platform_ioremap_resource()
clk: ti: Use devm_platform_get_and_ioremap_resource()
clk: mediatek: Convert to devm_platform_ioremap_resource()
clk: hsdk-pll: Convert to devm_platform_ioremap_resource()
clk: gemini: Convert to devm_platform_ioremap_resource()
clk: fsl-sai: Convert to devm_platform_ioremap_resource()
clk: bm1880: Convert to devm_platform_ioremap_resource()
clk: axm5516: Convert to devm_platform_ioremap_resource()
clk: actions: Convert to devm_platform_ioremap_resource()
clk: cdce925: Remove redundant of_match_ptr()
clk: pxa910: Move number of clocks to driver source
clk: pxa1928: Move number of clocks to driver source
clk: pxa168: Move number of clocks to driver source
clk: mmp2: Move number of clocks to driver source
...
These are all minor cleanups for platform specific code in arch/arm/
and some of the associated drivers. The majority of these are work
done by Rob Herring to improve the way devicetreee header files
are handled.
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Merge tag 'soc-arm-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC cleanups from Arnd Bergmann:
"These are all minor cleanups for platform specific code in arch/arm/
and some of the associated drivers. The majority of these are work
done by Rob Herring to improve the way devicetreee header files are
handled"
* tag 'soc-arm-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (49 commits)
ARM: davinci: Drop unused includes
ARM: s5pv210: Explicitly include correct DT includes
ARM: dove: Drop unused includes
ARM: mvebu: Explicitly include correct DT includes
Documentation/process: maintainer-soc: document dtbs_check requirement for Samsung
MAINTAINER: samsung: document dtbs_check requirement for Samsung
Documentation/process: maintainer-soc: add clean platforms profile
MAINTAINERS: soc: reference maintainer profile
ARM: nspire: Remove unused header file mmio.h
ARM: nspire: Use syscon-reboot to handle restart
soc: fsl: Explicitly include correct DT includes
soc: xilinx: Explicitly include correct DT includes
soc: sunxi: Explicitly include correct DT includes
soc: rockchip: Explicitly include correct DT includes
soc: mediatek: Explicitly include correct DT includes
soc: aspeed: Explicitly include correct DT includes
firmware: Explicitly include correct DT includes
bus: Explicitly include correct DT includes
ARM: spear: Explicitly include correct DT includes
ARM: mvebu: Explicitly include correct DT includes
...
The main change this time is the introduction of the drivers/genpd
subsystem that gets split out from drivers/soc to keep common
functionality together. Ulf Hansson is taking over maintainership for
these and is sending a separate pull request with the same commits,
but they are in the soc drivers tree to avoid conflicts against other
soc driver patches.
The SCMI driver subsystem gets an update to version 3.2 of the
specification. There are also updates to memory, reset and other firmware
drivers.
On the soc driver side, the updates are mostly cleanups across a number
of Arm platforms. On driver for loongarch adds power management for DT
based systems, another driver is for HiSilicon's Arm server chips with
their HCCS system health interface.
The remaining updates for the most part add support for additional
hardware in existing drivers or contain minor cleanups. Most of these
are for the Qualcomm Snapdragon platform.
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Merge tag 'soc-drivers-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"The main change this time was the introduction of the drivers/genpd
subsystem that gets split out from drivers/soc to keep common
functionality together.
The SCMI driver subsystem gets an update to version 3.2 of the
specification. There are also updates to memory, reset and other
firmware drivers.
On the soc driver side, the updates are mostly cleanups across a
number of Arm platforms. On driver for loongarch adds power management
for DT based systems, another driver is for HiSilicon's Arm server
chips with their HCCS system health interface.
The remaining updates for the most part add support for additional
hardware in existing drivers or contain minor cleanups. Most of these
are for the Qualcomm Snapdragon platform"
* tag 'soc-drivers-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (136 commits)
bus: fsl-mc: Use common ranges functions
soc: kunpeng_hccs: fix some sparse warnings about incorrect type
soc: loongson2_pm: add power management support
soc: dt-bindings: add loongson-2 pm
soc: rockchip: grf: Fix SDMMC not working on RK3588 with bus-width > 1
genpd: rockchip: Add PD_VO entry for rv1126
bus: ti-sysc: Fix cast to enum warning
soc: kunpeng_hccs: add MAILBOX dependency
MAINTAINERS: remove OXNAS entry
dt-bindings: interrupt-controller: arm,versatile-fpga-irq: mark oxnas compatible as deprecated
irqchip: irq-versatile-fpga: remove obsolete oxnas compatible
soc: qcom: aoss: Tidy up qmp_send() callers
soc: qcom: aoss: Format string in qmp_send()
soc: qcom: aoss: Move length requirements from caller
soc: kunpeng_hccs: fix size_t format string
soc: ti: k3-socinfo.c: Add JTAG ID for AM62PX
dt-bindings: firmware: qcom: scm: Updating VMID list
firmware: imx: scu-irq: support identifying SCU wakeup source from sysfs
firmware: imx: scu-irq: enlarge the IMX_SC_IRQ_NUM_GROUP
firmware: imx: scu-irq: add imx_scu_irq_get_status
...
and starts moving some of the corresponding code in there.
We have currently ~60 users of the genpd provider interface, which are
sprinkled across various subsystems. To release some burden from the soc
maintainers (Arnd Bergmann, etc) in particular, but also to gain a better
overall view of what goes on in the area, I will help out with maintenance.
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Merge tag 'genpd-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
Pull ARM SoC generic power domain driver updates from Ulf Hansson:
"This adds a new subsystem for generic power domain providers in
drivers/genpd and starts moving some of the corresponding code in
there.
We have currently ~60 users of the genpd provider interface, which are
sprinkled across various subsystems. To release some burden from the
soc maintainers (Arnd Bergmann, etc) in particular, but also to gain a
better overall view of what goes on in the area, I will help out with
maintenance"
[ I find the "genpd" name singularly uninformative, so we'll probably
end up moving this driver subsystem somewhere else, but that's still
being discussed - Linus ]
* tag 'genpd-v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm: (30 commits)
genpd: ti: Use for_each_node_with_property() simplify code logic
genpd: Explicitly include correct DT includes
genpd: imx: scu-pd: initialize is_off according to HW state
genpd: imx: scu-pd: Suppress bind attrs
genpd: imx: scu-pd: do not power off console if no_console_suspend
genpd: imx: scu-pd: add more PDs
genpd: imx: scu-pd: enlarge PD range
genpd: imx: relocate scu-pd under genpd
MAINTAINERS: adjust file entry in STARFIVE JH71XX PMU CONTROLLER DRIVER
genpd: Makefile: build imx
genpd: move owl-sps-helper.c from drivers/soc
soc: starfive: remove stale Makefile entry
ARM: ux500: Move power-domain driver to the genpd dir
ARM: ux500: Convert power-domain code into a regular platform driver
soc: xilinx: Move power-domain driver to the genpd dir
soc: ti: Mover power-domain drivers to the genpd dir
soc: tegra: Move powergate-bpmp driver to the genpd dir
soc: sunxi: Move power-domain driver to the genpd dir
soc: starfive: Move the power-domain driver to the genpd dir
soc: samsung: Move power-domain driver to the genpd dir
...
- Carve out the new CONFIG_LIST_HARDENED as a more focused subset of
CONFIG_DEBUG_LIST (Marco Elver).
- Fix kallsyms lookup failure under Clang LTO (Yonghong Song).
- Clarify documentation for CONFIG_UBSAN_TRAP (Jann Horn).
- Flexible array member conversion not carried in other tree (Gustavo
A. R. Silva).
- Various strlcpy() and strncpy() removals not carried in other trees
(Azeem Shaikh, Justin Stitt).
- Convert nsproxy.count to refcount_t (Elena Reshetova).
- Add handful of __counted_by annotations not carried in other trees,
as well as an LKDTM test.
- Fix build failure with gcc-plugins on GCC 14+.
- Fix selftests to respect SKIP for signal-delivery tests.
- Fix CFI warning for paravirt callback prototype.
- Clarify documentation for seq_show_option_n() usage.
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Merge tag 'hardening-v6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux
Pull hardening updates from Kees Cook:
"As has become normal, changes are scattered around the tree (either
explicitly maintainer Acked or for trivial stuff that went ignored):
- Carve out the new CONFIG_LIST_HARDENED as a more focused subset of
CONFIG_DEBUG_LIST (Marco Elver)
- Fix kallsyms lookup failure under Clang LTO (Yonghong Song)
- Clarify documentation for CONFIG_UBSAN_TRAP (Jann Horn)
- Flexible array member conversion not carried in other tree (Gustavo
A. R. Silva)
- Various strlcpy() and strncpy() removals not carried in other trees
(Azeem Shaikh, Justin Stitt)
- Convert nsproxy.count to refcount_t (Elena Reshetova)
- Add handful of __counted_by annotations not carried in other trees,
as well as an LKDTM test
- Fix build failure with gcc-plugins on GCC 14+
- Fix selftests to respect SKIP for signal-delivery tests
- Fix CFI warning for paravirt callback prototype
- Clarify documentation for seq_show_option_n() usage"
* tag 'hardening-v6.6-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux: (23 commits)
LoadPin: Annotate struct dm_verity_loadpin_trusted_root_digest with __counted_by
kallsyms: Change func signature for cleanup_symbol_name()
kallsyms: Fix kallsyms_selftest failure
nsproxy: Convert nsproxy.count to refcount_t
integrity: Annotate struct ima_rule_opt_list with __counted_by
lkdtm: Add FAM_BOUNDS test for __counted_by
Compiler Attributes: counted_by: Adjust name and identifier expansion
um: refactor deprecated strncpy to memcpy
um: vector: refactor deprecated strncpy
alpha: Replace one-element array with flexible-array member
hardening: Move BUG_ON_DATA_CORRUPTION to hardening options
list: Introduce CONFIG_LIST_HARDENED
list_debug: Introduce inline wrappers for debug checks
compiler_types: Introduce the Clang __preserve_most function attribute
gcc-plugins: Rename last_stmt() for GCC 14+
selftests/harness: Actually report SKIP for signal tests
x86/paravirt: Fix tlb_remove_table function callback prototype warning
EISA: Replace all non-returning strlcpy with strscpy
perf: Replace strlcpy with strscpy
um: Remove strlcpy declaration
...
