Remove mode_valid function, video modes should be checked in
encoder or bridge drivers.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
This is the 6.6.3 stable release
* tag 'v6.6.3': (526 commits)
Linux 6.6.3
drm/amd/display: Change the DMCUB mailbox memory location from FB to inbox
drm/amd/display: Clear dpcd_sink_ext_caps if not set
...
Signed-off-by: Jason Liu <jason.hui.liu@nxp.com>
Conflicts:
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
drivers/usb/dwc3/core.c
commit 8a32aa17c1 upstream.
The pointer to the next STI font is actually a signed 32-bit
offset. With this change the 64-bit kernel will correctly subract
the (signed 32-bit) offset instead of adding a (unsigned 32-bit)
offset. It has no effect on 32-bit kernels.
This fixes the stifb driver with a 64-bit kernel on qemu.
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This patch adds helper dprc_disable_repeat_en() so that callers
may disable DPRC repeat_en.
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Fast-forward imx8_dprc driver from imx_4.14.y.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Liu Ying: scfw call updates and other small tweaks for upgrade]
Fix plane settings including fb pixel format, address and pitch when
enabling crtc to avoid an initial corrupt frame.
Tested-by: Sandor Yu <Sandor.yu@nxp.com>
Cc: Sandor Yu <Sandor.yu@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds MPU interface(8080 mode) support in the LCDIF driver
so that LCDIF may send frames to the sec-dsim MIPI DSI controller embedded
in i.MX8mm/mn via that interface. From the MIPI DSI controller perspective,
the input interface is called S-i80(Synchronous i80 Interface).
The general idea is to leverage the self refresh(SR) helpers offered by the
DRM core to make the external display device enter self refresh mode and
hence disable LCDIF when appropriate. The relevant DRM connectors'
conn_state->self_refresh_aware flags are inspected to determine whether to
use MPU interface or DOTCLK interface(also called RGB interface).
Since LCDIF will be disabled when the self refresh is active and the data
is transferred at modest rate, there are below known limitations:
1) The cur_frame_done interrupt comes at a lower frequency than the
display vsync signal frequency due to the low data transfer rate.
So, vblank events cannot reflect the real vsync pulses of the external
display.
2) Screen tearing phenomenon can be seen, because the frame update is
asynchronous to the external display self refresh and the LCDIF
controller does not support the 'Tearing Effect' mechanism.
3) The fbdev emulation and boot logo can not be updated onto screen in
time, because the external display often enters self refresh mode at
those stages. The boot logo will show up until the next time when
frame is sent to the external display via the MPU interface, e.g., when
the next framebuffer pan display operation is done after the logo is
ready in framebuffer. Like the below command line, writing to the
framebuffer sys node 'pan' frequently at background may make the
framebuffer emulation be a bit responsive.
while true; do echo 0,0 > /sys/class/graphics/fb0/pan; sleep 1; done &
Cc: Sandor Yu <Sandor.yu@nxp.com>
Cc: Wujian sun <wujian.sun_1@nxp.com>
Reviewed-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add mode_valid() implementation for CRTC to filter out any
mode which cannot be supported by LCDIF. Only check the
CEA and DMT modes for pixel clock round rate is same with
the value from mode.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
(cherry picked from commit d9be4b3d3b)
[ Liu Ying: Squash a build fix due to rebase upon v5.19-rc7 ]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Add mode_valid() implementation for CRTC to filter out any
mode which cannot be supported by LCDIFv3. Only check the
CEA and DMT modes for pixel clock round rate is same with
the value from mode.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
[ Liu Ying: Squash a build fix due to rebase upon v5.19-rc7 ]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
After the atomic plane update, the shadow load should be
enabled to make sure its update can take effect on next
frame in any cases. And this enable is better to be done
in CRTC's atomic_flush() which is called after plane's
atomic_update() is called.
Besides, the shadow load enable in controller enable is
unnecessary, so remove it.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
The LCDIFv3 core driver is responsible to provide
controller registers configuration and create the
platform devices for the child port nodes. And the
platform devices later will attach to the related
DRM/KMS drivers via name match. And the LCDIFv3 is
completely different from the LCDIF controller
which is used on imx8mm and imx8mn platforms.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
[ Liu Ying: Remove drm_get_format_name() ]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
According to LCDIF specification, the input pixel data
width and the output pixel data width can be different,
and this conversion is done by LCDIF automatically. So
config the output data width according to the requested
bus format from the encoder, instead to be same with the
input pixel data width.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit bfd27f6d71d86a7f2fc8314f082565db3682b925)
According to the LCDIF specification, the Legacy Mode does not
support cropping function in the horizontal direction, so add
Pigeon Mode which can support this kind of function. And when
enable this mode, the legacy horizontal timings configuration
should use stride value but not the active width, and related
pigeon configuration should use the active width but not the
stride value.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit e6da9542693dd585972897f62748a101f5726a74)
Add an function to get the LCDIF controller supported bus
formats according to the pixel format bpp. And change the
bus format sanity check in the plane's atomic check to see
if the bus format required by the peripheral attached to
LCDIF can be supported by LCDIF.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
The LCDIF core driver is responsible to provide controller
registers configuration and create the platform devices for
the child port nodes. And the platform devices later will
attach to the corresponding DRM/KMS drivers via name match.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
[ Aisheng: Kconfig & Makefile update for a clean base ]
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
[ Liu Ying: Remove drm_get_format_name() ]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Liu Ying: Rename driver from imx-lcdif to imx8mm-lcdif ]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Liu Ying: Use SET_LATE_SYSTEM_SLEEP_PM_OPS ]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
[ Liu Ying: Change CONFIG_IMX_LCDIF_CORE to CONFIG_IMX8MM_LCDIF_CORE ]
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds user-configurable CRC region support.
The users may choose a region of interest(ROI) as the CRC source
(i.e., the CRC evaluation window) via the debugfs control node.
The ROI cannot exceed the display region as indicated by
drm_crtc_state->adjusted_mode. The users may write a string in
the fashion of "roi:x1,y1,x2,y2" to the node to specify the ROI
within the display region. The inclusive position at (x1, y1)
indicates the upper left of the region, while the exclusive
position at (x2, y2) indicates the lower right of the region.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
This patch adds helper disengcfg_sig_select() support so that
users may select different taps(FrameGen, GammaCor, Matrix or
Dither) to do signature computation. Also, select FrameGen as
the default tap in _dpu_dec_init() and call it in dpu_dec_init().
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
This patch adds signature unit support in the dpu common driver.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Reviewed-by: Robby Cai <robby.cai@nxp.com>
As DPU fetchunits support ITU601(limited range)/ITU601_FR(full range)
and ITU709(limited range) YUV to RGB color space conversions, we may
add color encoding and color range properties support for planes.
Considering software backward compatibility, the default color encoding
is set to ITU601 with full color range.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds mulitple pixel blend modes for DPU plane.
The modes are "None", "Pre-multiplied" and "Coverage".
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Without the new blend modes("None", "Pre-multiplied" and "Coverage")
introduced in the below commit, the old userspace assumes alpha in
pixel is per-premultiplied by default. So, let's support the default
blend mode properly.
commit a5ec8332d4 ("drm: Add per-plane pixel blend mode property")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_pixengcfg_syncmode_master() helper support
so that the callers may control if a extdst is master or slave
when it works in sync mode. The bit16 of extdst's PIXENGCFG_STATIC
register controls this and it's a part of sync mode fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit7 of framegen's SECSTATCONFIG register is used to control
the sync mode fixup logic implemented in framegen. This patch
adds framegen_syncmode_fixup() helper so that the callers
may enable/disable the fixup logic for a framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Store9 unit can be shared bewteen display engine(for sync mode fixup)
and blit engine. It's proper to get the store resource in the DPU
common driver and then provide it to client platform device via
platform data.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9. So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds pixel combiner support in the DPU core driver.
Users may get and enable/disable/control a pixel combiner instant
via tcon functions and may tell if it is needed in a specific usecase
via the dpu_get_syncmode_min_prate() and dpu_get_singlemode_max_width()
helpers.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for tcon so that
two tcons can participate in the dual display streams
to work with pixel combiner to drive a high pixel rate
display.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds side-by-side support for framegen so that
two framegens can work in sync mode to participate in the
dual display streams to drive a high pixel rate display
via a pixel combiner.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds tcon_is_master/slave() helpers support so that
callers may know if a tcon is a master or slave tcon.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds extdst_is_master() helper support so that
callers may know if a extdst is a master extdst or not.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds framegen_is_master/slave() helpers support so that
callers may know if a framegen is a master or slave framegen.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds helper dpu_get_master_stream_id() support
so that callers may know the master stream when FrameGen
works in sync mode.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds a new di_grp_id entry in display client pdev's data
so that the relevant display platform driver may know the display
group ID of the display device.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
The CRTC background should be full screen instead of partial
screen, because the DRM core is likely to add configurable
background color support in the future. We may cover the full
screen with ConstFrame0/1, upon which builds planes. With this,
it is easier to compute each plane's layer offset vs CRTC start
point and all ConstFrame units can be controlled by CRTC.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
This patch adds two helpers to get and clear FrameGen secondary channel
status respectively. Via the two helpers, users may know if there is
empty FIFO read request on this channel or not after getting the status.
And, if yes, users may choose to clear the status. According to the IP
spec, the empty FIFO read request indicates that data stream from a Fetch
unit(e.g., AXI bandwidth not sufficient) fell down. Assuming the display
driver sets things up properly, the falling down is very likely caused by
the insufficient AXI bandwidth, that is, display underrun.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
To workaround the errata TKT320950, DPR/PRG need to evade the first dumb frame
which is generated by DPU. The way we achieve that is to bypass TCON(but set
the TCON sync signals and KA_CHUCK strobe signal up) before enabling the DPU
display controller, and then 1) enable the display controller, 2) wait for the
frame index starting to move and 3) finally switch TCON to operation mode.
Steps 1) to 3) should be done within a frame, so we disable local irq and
preemption to make sure we don't relinquish CPU during the procedure.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
