Sometimes retries exceed 500 and cause V2X suspend/resume
to fail occasionally
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Add a new imx943-evk-sgmii.dts to support 1G/2.5G SGMII ports on imx943-evk
board. The default dts is used to support MII.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
To support GPY215C on imx943 evk board, built in this driver by default.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
The PCS/PHY used by mx94 is similar to mx95, but there are the following
differences:
1) Only supports 1G SGMII and 2.5G SGMII
2) There are two lanes supported, both supporting up to 2.5G SGMII
Since two lanes need to be configured separately, unlike iMX95 only has
one lane, after configuring one lane, if need to configure another lane,
need to unlock the hardware lock used to configure the first lane before
configuring the second lane normally.
Therefore, the locking and unlocking process of xpcs phy hardware lock
is optimized.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Although the iMX943's XPCS and PHY versions are different from mx95,
their XPCS/PHY IDs are exactly the same as mx95.
So, the two versions cannot be distinguished by ID.
Therefore, pass in version when calling xpcs_create_mdiodev_with_phy()
to distinguish them.
Since the PCS and PHY of iMX943 support two lanes, portid needs to be
configured in PHY when configuring different lanes.
Therefore, portid is also passed to the xpcs_create_mdiodev_with_phy()
function for corresponding configuration.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Add xpcs port init API to init the different lane of xpcs and serdes.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Add NETC Switch support, both swp0 and swp1 work at MII mode, and
swp2 works at RGMII mode. Also enable NETC Timer instance 0 to
support PTP for switch.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Enable DSA and NETC_SWITCH.
Enable redirect and generic actions for NETC Switch.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Currently, suspend/resume of NETC Switch is not fully supported. This is
just a temporary patch to solve the call trace and crash problems caused
by Switch during system suspend/resume. There is no reason to block the
system suspend/resume process due to the switch problem. So this is a
quick fix and full support will be added in the future.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The statistics of each user port can be obtained through ethtool,
but the statistics of the CPU port cannot be obtained by ethtoll.
Besides, ethtool obtains many statistical values, but only a few
key statistical values are needed in the actual debugging process.
To facilitate debugging, the debugfs interface is added to obtain
key statistical information of the specified port.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The switch supports both one-step and two-step timestamp. For ingress
PTP packets, the filtering rules are set to redirect them to the CPU
port via the ingress port filter table. And the capture timestamp is
recorded in the switch tag (To_Host tag, subType=1).
For egress PTP packets, the switch tag(To_Port tag) is used to specify
whether to perform one-step timestamping (subType=1)or two-step
timestamping (subType=2). If two-step timestamping is performed, the
switch automatically generates a response packet to record the transmit
timestamp in the switch tag (To_Host tag, subType=2) and sends this
response packet to the CPU port.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Some functions of NETC Switch are configured through registers, and some
functions are configured through various tables. To facilitate debugging,
we added the debugfs interfaces to dump relevant registers and tables
information.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Add a generic debugfs interface to netc-lib to show the information
about the IPFT flower, which will be used by both ENETC driver and
NETC Switch driver.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
In the previous patch, FLOW_ACTION_POLICE needs to be used with
FLOW_ACTION_TRAP or FLOW_ACTION_REDIRECT. In some scenarios, only rate
limit may be required, so the support of FLOW_ACTION_POLICE is added
separately.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Since both ENETC and Switch support ingress port filter table (IPFT),
and the IPFT can be used for stream police. So add the related APIs
to netc-lib, so that these generic APIs can be used by enetc driver
and switch driver.
Example command for configruing POLICE:
tc qdisc add dev swp0 clsact
tc filter add dev swp0 ingress flower skip_sw dst_mac \
52:8e:e6:f1:9d:f1 action police mtu 2000 rate 100mbit burst 100k \
conform-exceed drop
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
For FLOW_ACTION_TRAP, the matched frames received will be redirected to
the CPU port.
For FLOW_ACTION_REDIRECT, the matched frames received will be redirected
to a specified switch port.
In addition, it also supports POLICE action with TRAP or REDIRECT action.
Example command for configuring REDIRECT:
tc qdisc add dev swp0 clsact
tc filter add dev swp0 ingress flower skip_sw dst_mac 66:9E:7D:89:9A:03 \
action mirred egress redirect dev swp1
Example command for configuring TRAP:
tc qdisc add dev swp0 clsact
tc filter add dev swp0 ingress chain 21000 protocol 802.1Q flower \
skip_sw dst_mac 16:80:31:29:90:18 vlan_ethtype ipv4 vlan_id 100 \
vlan_prio 0 action trap
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Both ENETC and Switch support ingress port filter table, so add
a common interface netc_ipft_keye_construct() to the netc-lib,
which converts flow_rule to ipft_keye_data.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The NETC switch supports per stream filtering and policing (PSFP), and
this feature is implemented based on IEEE 802.1Qci.
Currently, the stream identification only supports two methods: DMAC +
VLAN and SMAC + VLAN. This is not a hardware limitation, but the current
driver uses a relatively simple method to implement this feature. In the
future, the ingress port filter table will be introduced to support more
accurate stream identification.
Example for PSFP with hardware offload:
tc qdisc add dev swp1 ingress
tc filter add dev swp1 parent ffff: protocol 802.1Q chain 1 flower \
skip_sw src_mac 00:04:9f:08:dc:5b vlan_ethtype ipv4 vlan_id 100 \
vlan_prio 6 action gate index 1 base-time 100000 sched-entry open \
800000 1 -1 sched-entry close 800000 -1 -1 action police mtu 2000 \
rate 20mbit burst 100k conform-exceed drop
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The NETC Switch supports time based transmission mechanism, which is
implemented based on IEEE 802.1Qbv. Each traffic class has a gate, which
controls if the traffic class is open or closed. Only frames in traffic
classes with open gate are eligible for transmission. The gate state in
each traffic class is controlled by the gate control list. A gate control
list consists of an ordered list of gate control entries, where each
entry specifies an 8 bit gate state vector where each bit (one per gate),
indicates whether the gate is open or closed. The gate control entry also
specifies the time duration for the states.
Example for TAPRIO with hardware offload:
tc qdisc replace dev swp0 parent root handle 200 taprio num_tc 8 \
map 0 1 2 3 4 5 6 7 queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \
base-time 100000 sched-entry S ff 80000 sched-entry S 00 80000 \
max-sdu 1000 1000 1000 1000 1000 1000 1000 1000 flags 0x2
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
TMR_CUR_TIME registers are used to get the current time, the time is
calculated by adding TMROFF_H/L with TMR_CNT_H/L register. Currently,
the TMROFF_H/L register is not used and its default value is 0, so
the value read from TMR_CNT registers is the same as TMR_CUR_TIME_H/L.
However, in order to prevent the potential issue caused by the use of
the TMROFF_H/L register in the future, it is best to use TMR_CUR_TIME
registers to obtain the current time from now on.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The NETC switch supports IEEE 802.1Qbu preemption. A physical port which
supports preemption contains 2 MACs (MAC 0 and 1). When frame preemption
is enabled, MAC 0 handles express traffic, and MAC 1 handles preemptible
traffic. The two MACs are merged on one port as defined in 802.3 Clause
99.
Example command for configuring 802.1Qbu:
tc qdisc add dev swp0 parent root handle 100: mqprio num_tc 8 \
map 0 1 2 3 4 5 6 7 queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \
fp P P P P E E E E hw 1
ethtool --set-mm swp0 verify-enabled off tx-enabled on \
pmac-enabled on
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The Credit-based Shaper (CBS) is implemented as per IEEE 802.1Qav, which
is needed for applications requiring bandwidth allocation. The CBS acts
independently, per traffic class, to control the bandwidth distribution
between normal traffic and time-sensitive traffic with respect to the
total link bandwidth available. In order for the CBS algorithm to operate
as intended, it is necessary for all traffic classes that support the
algorithm to be numerically higher than any traffic classes that support
the strict priority algorithm.
The switch has 8 traffic classes, CBS should be enabled on numerically
highest traffic class(es).so a maximum of 7 traffic classes is supported
with CBS enabled. However, only traffic class 6 and 7 support to enable
CBD in the current, other low-priority traffic classes do not support it.
Example command for configuring CBS offload (port speed is 100Mbps):
tc qdisc add dev swp0 parent root handle 100: mqprio num_tc 8 \
map 0 1 2 3 4 5 6 7 queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 hw 1
tc qdisc replace dev swp0 parent 100:8 cbs idleslope 10800 \
sendslope -89200 hicredit 12 locredit -113 offload 1
tc qdisc replace dev swp0 parent 100:7 cbs idleslope 20700 \
sendslope -79300 hicredit 153 locredit -1389 offload 1
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
NETC switch supports maximum 8 TCs, to simplify the implementation,
only one TXQ per TC is supported. In addition, the preemptible_tcs
field in struct tc_mqprio_qopt_offload is not supported at preset,
it will be supported in a subsequent patch.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The buffer pool is a quantity of memory available for buffering a group
of flows (e.g. frames having the same priority, frames received from the
same port), while waiting to be transmitted on a port. The buffer pool
tracks internal memory consumption with upper bound limits and optionally
a non-shared portion when associated with a shared buffer pool. Currently
the shared buffer pool has not been associated with the buffer pool. We
will add the shared buffer pool support in the future. In addition, the
flow control feature of the switch is also implemented through the buffer
pool.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Add basic switch functions support, such as FDB table, VLAN filter and
table and so on.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
NETC provides full 802.1Q Ethernet switch functionality, advanced QoS
with 8 traffic classes and 4 drop resilience levels, and a full range
of TSN standards capabilities. The current patch only introduces the
NETC Switch driver and provides only the probe/remove interfaces. The
complete functionality will be supported by subsequent patches.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The NXP switch tag is a proprietary header added to frames after the
source MAC address. The switch tag has 3 types, and different types
have multiple subtypes, the details are as follows.
- Forward NXP switch tag (Type=0) – Represents forwarded frames.
- SubType=0 - Normal frame processing.
- To_Port NXP switch tag (Type=1) – Represents frames that are to be
sent to a specific switch port.
- SubType=0 - No request to perform timestamping.
- SubType=1 - Request to perform one-step timestamping.
- SubType=2 - Request to perform two-step timestamping.
- To_Host NXP switch tag (Type=2) – Represents frames redirected or
copied to the switch management port.
- SubType=0 - Received frames redirected or copied to the switch
management port.
- SubType=1 - Received frames redirected or copied to the switch
management port with captured timestamp at the switch port where
the frame was received.
- SubType=2 - Transmit timestamp response (two-step timestamping).
Therefore, the length of different type switch tag is different, the
minimum length is 6 bytes, the maximum length is 14 bytes.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Add buffer pool table and shared buffer pool table support.
The Buffer Pool table contains buffer pool configuration and operational
information. Each entry corresponds to a buffer pool.
The Shared Buffer Pool table contains shared buffer pool configuration
and operational information. Each entry corresponds to a shared buffer
pool.
A buffer pool is a quantity of memory available for buffering a group
of flows (e.g. frames having the same priority, frames received from
the same port), while waiting to be transmitted on a port. A buffer
pool tracks internal memory consumption with upper bound limits and
optionally a non-shared portion when associated with a shared buffer
pool.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Ingress and egress frame modification actions are specified in this
table if Frame Modification entry ID (FM_EID) is used as an index.
This table is implemented as a linear array of words, accessed using
an index (0, 1, 2, ..., n) that uniquely identifies a word within the
array. For this table, each table entry occupies one word (one to one
corresponding between words and entries).
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Egress related statistics are maintained in this table. The Egress
Count table is implemented as a linear array of entries accessed
using an index (0, 1, 2, ..., n) that uniquely identifies an entry
within the array. Egress Counter Entry ID (EC_EID) is used as an
index to an entry in this table. The EC_EID is specified in the
Egress Treatment table. Egress Count table entries are always
present and enabled.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The Egress Sequence Recovery table contains one entry per FRER recovery
function (implemented as per 802.1CB), and each entry contains a number
of configuration elements, whose value is set when the table entries are
configured, and operational elements, which are managed by the hardware
and can be queried by software. Whether or not a FRER recovery function
is to be performed is specified in the Egress Treatment table, and if so
then the Egress Treatment table also provides an index into a Egress
Sequence Recovery table.
The Egress Sequence Recovery table is implemented as a linear array of
entries accessed using an index (0,1, 2, ..., n) that uniquely identifies
an entry within the array.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Each entry in the Egress Treatment table contains the egress packet
processing actions to be applied to a grouping or scope of packets
exiting on a particular egress port of the switch. A scope of packets,
for example, could be the packets exiting a particular VLAN, matching
a particular 802.1Q bridge forwarding entry or belonging to a stream
identified at ingress. The Egress Treatment table is implemented as a
linear array of entries accessed using an index (0,1, 2, ..., n) that
uniquely identifies an entry within the array.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The VLAN filter table contains configuration and control information for
each VLAN configured on the switch. Each VLAN entry includes the VLAN
port membership, which FID to use in the FDB lookup, which spanning tree
group to use, the egress frame modification actions to apply to a frame
exiting form this VLAN, and various configuration and control parameters
for this VLAN.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
The FDB table is used for MAC learning lookups and MAC forwarding lookups.
Each table entry includes information such as a FID and MAC address that
may be unicast or multicast and a forwarding destination field containing
a port bitmap identifying the associated port(s) with the MAC address.
FDB table entries can be static or dynamic. Static entries are added from
software whereby dynamic entries are added either by software or by the
hardware as MAC addresses are learned in the datapath.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
During system PM, if no wakeup requirement, disable transceiver,
this can save power.
Reviewed-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Enable netc_timer1 to make NETC default synchronous clock work.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
imx95 has only one timer, so a fixed timer configuration is used in
the driver.
On imx94, there are a total of 3 timers. Therefore, it is necessary
to determine which timer to use based on the configuration of dts.
Add nxp,ptp-timer property to decide which timer to use.
If this property does not exist, the default configuration will be
used. The default configuration may be not usable if the timer is
not enabled in dts.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Synchronize parameters used by netc_timer_get_phc_index() with upstream
versions.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
To support DP83848 on imx943 evk board, built in this driver by default.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Add the config set RMII mode when the interface is returned RMII mode.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
As IT6263 is the default bridge for i.MX943, remove the overlay dtb and
add the display and it6263 nodes to the main dtbs.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Acked-by: Liu Ying <victor.liu@nxp.com>
iMX94 has special muxing options for certain pins. Add new vendor
defined pinctrl type to SCMI pinctrl driver to handle these pins.
The MUX value field in the IOMUX table is extended to 16 bits where
the lower 8 bits represent the current IOMUX value and the upper
8 bits represent the new extended mux added in iMX94.
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
pinctrl config
iMX94 has special muxing options for certain pins.
The MUX value field in the IOMUX table is extended to 16 bits where
the lower 8 bits represent the current IOMUX value and the upper
8 bits represent the new extended mux added in iMX94.
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Add the i.MX943 DCIF driver to the config and also enable the upstream
FSL_LDB driver.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Acked-by: Liu Ying <victor.liu@nxp.com>
In order to use the upstream LDB driver for our new platforms (i.MX94),
yet not break the old i.MX93 boards, the downstream i.MX93 LDB driver
compatible has been renamed. Change it.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
Since there is an upstream LDB driver that's compatible with i.MX93,
let's rename the downstream driver compatible in order to be able to use
both drivers for different platforms until we phase out the downstream
one.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
There is an upstream driver now with the same "fsl,imx93-ldb"
compatible. Rename the downstream driver compatible to be able to use
both drivers with our platforms.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
