4119f0dfbd
Unfortunately, (R) and (W) are valid markups for enumerated lists, as described at: https://docutils.sourceforge.io/docs/ref/rst/restructuredtext.html#enumerated-lists So, we ned to replace them by: (R) -> (Read) (W) -> (Write) As otherwise, (R) will be displayed as R., with is not what it is desired. There's no need to touch (RO) and (RW). Acked-by: Jonathan Corbet <corbet@lwn.net> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/6e81ad8064f3ed4f8dc265086fdf1c618043f935.1604042072.git.mchehab+huawei@kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2.2 KiB
What: /sys/bus/coresight/devices/<memory_map>.stm/enable_source Date: April 2016 KernelVersion: 4.7 Contact: Mathieu Poirier mathieu.poirier@linaro.org Description: (RW) Enable/disable tracing on this specific trace macrocell. Enabling the trace macrocell implies it has been configured properly and a sink has been identified for it. The path of coresight components linking the source to the sink is configured and managed automatically by the coresight framework.
What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_enable Date: April 2016 KernelVersion: 4.7 Contact: Mathieu Poirier mathieu.poirier@linaro.org Description: (RW) Provides access to the HW event enable register, used in conjunction with HW event bank select register.
What: /sys/bus/coresight/devices/<memory_map>.stm/hwevent_select Date: April 2016 KernelVersion: 4.7 Contact: Mathieu Poirier mathieu.poirier@linaro.org Description: (RW) Gives access to the HW event block select register (STMHEBSR) in order to configure up to 256 channels. Used in conjunction with "hwevent_enable" register as described above.
What: /sys/bus/coresight/devices/<memory_map>.stm/port_enable Date: April 2016 KernelVersion: 4.7 Contact: Mathieu Poirier mathieu.poirier@linaro.org Description: (RW) Provides access to the stimulus port enable register (STMSPER). Used in conjunction with "port_select" described below.
What: /sys/bus/coresight/devices/<memory_map>.stm/port_select Date: April 2016 KernelVersion: 4.7 Contact: Mathieu Poirier mathieu.poirier@linaro.org Description: (RW) Used to determine which bank of stimulus port bit in register STMSPER (see above) apply to.
What: /sys/bus/coresight/devices/<memory_map>.stm/status Date: April 2016 KernelVersion: 4.7 Contact: Mathieu Poirier mathieu.poirier@linaro.org Description: (Read) List various control and status registers. The specific layout and content is driver specific.
What: /sys/bus/coresight/devices/<memory_map>.stm/traceid Date: April 2016 KernelVersion: 4.7 Contact: Mathieu Poirier mathieu.poirier@linaro.org Description: (RW) Holds the trace ID that will appear in the trace stream coming from this trace entity.