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The ReST format requires blank lines before/after identation changes,
for it to properly detect lists.
Fixes: ee7abc105e
("platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file")
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/3673e1a255ad4100c933af215b60d68ba126f820.1632740376.git.mchehab+huawei@kernel.org
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
816 B
816 B
What: /sys/devices/platform//etr3 Date: Apr 2021 KernelVersion: 5.13 Contact: "Tomas Winkler" tomas.winkler@intel.com Description: The file exposes "Extended Test Mode Register 3" global reset bits. The bits are used during an Intel platform manufacturing process to indicate that consequent reset of the platform is a "global reset". This type of reset is required in order for manufacturing configurations to take effect.
Display global reset setting bits for PMC.
* bit 31 - global reset is locked
* bit 20 - global reset is set
Writing bit 20 value to the etr3 will induce
a platform "global reset" upon consequent platform reset,
in case the register is not locked.
The "global reset bit" should be locked on a production
system and the file is in read-only mode.