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d6b4952355
Design team says that the frequency limitation mentioned at controller specification is just a general guideline for the IP. The maximum frequency depends on the process technology and SoC architecture requirement of the SoC. Specifically for i.MX95, the frequency of dspx_clk is signed off at 350MHz at UD/NM/OD mode. So 350MHz is the limit of the chip, not 300MHz. So, change maximum FrameGen display clock frequency from 300MHz to 350MHz. Reported-by: Qiang Li <qiang.li@nxp.com> Reviewed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Acked-by: Jason Liu <jason.hui.liu@nxp.com> |
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| .. | ||
| dcnano | ||
| dcss | ||
| dpu | ||
| dpu95 | ||
| ipuv3 | ||
| lcdc | ||
| lcdif | ||
| lcdifv3 | ||
| mhdp | ||
| dw_hdmi-imx.c | ||
| dw_mipi_dsi-imx.c | ||
| imx-drm-core.c | ||
| imx-drm.h | ||
| imx-ldb.c | ||
| imx-tve.c | ||
| imx8mp-hdmi-pavi.c | ||
| imx8mp-hdmi-pavi.h | ||
| imx8mp-ldb.c | ||
| imx8qm-ldb.c | ||
| imx8qxp-ldb.c | ||
| imx93-ldb.c | ||
| imx93-parallel-disp-fmt.c | ||
| Kconfig | ||
| lcdif-mux-display.c | ||
| Makefile | ||
| parallel-display.c | ||
| sec_mipi_dphy_ln14lpp.h | ||
| sec_mipi_dsim-imx.c | ||
| sec_mipi_pll_1432x.h | ||