f172a63d70
Because imx93_lpm needs to call ELE API, so adding the IMX_SEC_ENCLAVE dependency to avoid build issue. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
2.4 KiB
SPDX-License-Identifier: GPL-2.0-only
menu "i.MX SoC drivers"
config IMX_GPCV2_PM_DOMAINS bool "i.MX GPCv2 PM domains" depends on ARCH_MXC || (COMPILE_TEST && OF) depends on PM select PM_GENERIC_DOMAINS select REGMAP_MMIO default y if SOC_IMX7D
config SOC_IMX8M tristate "i.MX8M SoC family support" depends on ARCH_MXC || COMPILE_TEST default ARCH_MXC && ARM64 select SOC_BUS select ARM_GIC_V3 if ARCH_MXC && ARCH_MULTI_V7 help If you say yes here you get support for the NXP i.MX8M family support, it will provide the SoC info like SoC family, ID and revision etc.
config IMX8M_BUSFREQ tristate "i.MX8M busfreq" depends on SOC_IMX8M default ARCH_MXC
config IMX8M_PM_DOMAINS tristate "i.MX8M PM domains" default ARCH_MXC depends on ARCH_MXC || (COMPILE_TEST && OF) depends on PM select PM_GENERIC_DOMAINS
config SOC_IMX9 tristate "i.MX9 SoC family support" depends on ARCH_MXC || COMPILE_TEST depends on IMX_SEC_ENCLAVE default ARCH_MXC && ARM64 select SOC_BUS help If you say yes here, you get support for the NXP i.MX9 family
config IMX8M_BLK_CTRL bool default SOC_IMX8M && IMX_GPCV2_PM_DOMAINS depends on PM_GENERIC_DOMAINS depends on COMMON_CLK
config IMX9_BLK_CTRL bool default SOC_IMX9 && IMX_GPCV2_PM_DOMAINS depends on PM_GENERIC_DOMAINS
config SECVIO_SC tristate "NXP SC secvio support" depends on IMX_SCU default y help If you say yes here you get support for the NXP SNVS security violation module. It includes the possibility to read information related to security violations and tampers. It also gives the possibility to register user callbacks when a security violation occurs.
config RPMSG_LIFE_CYCLE tristate "i.MX8ULP Rpmsg Life Cycle Support" depends on ARCH_MXC || COMPILE_TEST depends on RPMSG default ARCH_MXC && ARM64 help If you say yes here you get supoort for the rpmsg life cycle support on i.MX8ULP for low power mode state coordination between A core & M core to make sure A core can be put into Low power mode without risk by sending notify to M core.
config IMX8ULP_LPM_CTRL tristate "i.MX8ULP DDR Low Power Control support" depends on ARCH_MXC || COMPILE_TEST default ARCH_MXC && ARM64 help If you say yes here you get supoort for DDR frequency scaling support on i.MX8ULP for scaling the DDR frequency based on user case. The DDR frequency need to be switched manually by user. endmenu