fdc0074c5f
As the sunxi usb clocks all contain a reset controller, it is not
possible to build the sunxi clock driver without RESET_CONTROLLER
enabled. Doing so results in an undefined symbol error:
drivers/built-in.o: In function `sunxi_gates_clk_setup':
linux/drivers/clk/sunxi/clk-sunxi.c:1071: undefined reference to
`reset_controller_register'
This is possible if building a minimal kernel without PHY_SUN4I_USB.
The dependency issue is made visible at compile time instead of
link time by the new A80 mmc clocks, which also use a reset control
itself.
This patch makes ARCH_SUNXI select ARCH_HAS_RESET_CONTROLLER and
RESET_CONTROLLER.
Fixes: 559482d1f9 ARM: sunxi: Split the various SoCs support in Kconfig
Cc: <stable@vger.kernel.org> # 3.16+
Reported-by: Lourens Rozema <ik@lourensrozema.nl>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
969 B
menuconfig ARCH_SUNXI bool "Allwinner SoCs" if ARCH_MULTI_V7 select ARCH_REQUIRE_GPIOLIB select ARCH_HAS_RESET_CONTROLLER select CLKSRC_MMIO select GENERIC_IRQ_CHIP select PINCTRL select SUN4I_TIMER select RESET_CONTROLLER
if ARCH_SUNXI
config MACH_SUN4I bool "Allwinner A10 (sun4i) SoCs support" default ARCH_SUNXI
config MACH_SUN5I bool "Allwinner A10s / A13 (sun5i) SoCs support" default ARCH_SUNXI select SUN5I_HSTIMER
config MACH_SUN6I bool "Allwinner A31 (sun6i) SoCs support" default ARCH_SUNXI select ARM_GIC select MFD_SUN6I_PRCM select SUN5I_HSTIMER
config MACH_SUN7I bool "Allwinner A20 (sun7i) SoCs support" default ARCH_SUNXI select ARM_GIC select ARM_PSCI select HAVE_ARM_ARCH_TIMER select SUN5I_HSTIMER
config MACH_SUN8I bool "Allwinner A23 (sun8i) SoCs support" default ARCH_SUNXI select ARM_GIC select MFD_SUN6I_PRCM
config MACH_SUN9I bool "Allwinner (sun9i) SoCs support" default ARCH_SUNXI select ARM_GIC
endif