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linux-watchdog 6.12-rc1 tag
-----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.14 (GNU/Linux) iEYEABECAAYFAmbv6AcACgkQ+iyteGJfRsqKdgCgr3VyhlkM+ryZtxnYl02midaC Yp4An2baWN7fzdJWgj11coglnM/mpGvG =J3w7 -----END PGP SIGNATURE----- Merge tag 'linux-watchdog-6.12-rc1' of git://www.linux-watchdog.org/linux-watchdog Pull watchdog updates from Wim Van Sebroeck: - Add Watchdog Timer driver for RZ/V2H(P) - Add Cirrus EP93x - Some small fixes and improvements * tag 'linux-watchdog-6.12-rc1' of git://www.linux-watchdog.org/linux-watchdog: watchdog: Convert comma to semicolon watchdog: rzv2h_wdt: Add missing MODULE_LICENSE tag to fix modpost error dt-bindings: watchdog: Add Cirrus EP93x dt-bindings: watchdog: stm32-iwdg: Document interrupt and wakeup properties drivers: watchdog: marvell_gti: Convert comma to semicolon watchdog: iTCO_wdt: Convert comma to semicolon watchdog: Add Watchdog Timer driver for RZ/V2H(P) dt-bindings: watchdog: renesas,wdt: Document RZ/V2H(P) SoC watchdog: imx_sc_wdt: detect if already running watchdog: imx2_wdt: Remove __maybe_unused notations watchdog: imx_sc_wdt: Don't disable WDT in suspend watchdog: imx7ulp_wdt: move post_rcs_wait into struct imx_wdt_hw_feature
This commit is contained in:
Linus Torvalds
commit
f34c512521
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@ -0,0 +1,42 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/watchdog/cirrus,ep9301-wdt.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cirrus Logic EP93xx Watchdog Timer
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maintainers:
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- Nikita Shubin <nikita.shubin@maquefel.me>
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- Alexander Sverdlin <alexander.sverdlin@gmail.com>
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allOf:
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- $ref: watchdog.yaml#
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properties:
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compatible:
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oneOf:
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- const: cirrus,ep9301-wdt
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- items:
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- enum:
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- cirrus,ep9302-wdt
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- cirrus,ep9307-wdt
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- cirrus,ep9312-wdt
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- cirrus,ep9315-wdt
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- const: cirrus,ep9301-wdt
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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watchdog@80940000 {
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compatible = "cirrus,ep9301-wdt";
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reg = <0x80940000 0x08>;
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};
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@ -75,6 +75,8 @@ properties:
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- renesas,r8a779h0-wdt # R-Car V4M
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- const: renesas,rcar-gen4-wdt # R-Car Gen4
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- const: renesas,r9a09g057-wdt # RZ/V2H(P)
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reg:
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maxItems: 1
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@ -113,7 +115,6 @@ properties:
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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allOf:
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@ -137,6 +138,7 @@ allOf:
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compatible:
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contains:
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enum:
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- renesas,r9a09g057-wdt
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- renesas,rzg2l-wdt
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- renesas,rzv2m-wdt
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then:
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@ -171,6 +173,19 @@ allOf:
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interrupts:
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maxItems: 1
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a09g057-wdt
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then:
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properties:
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interrupts: false
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interrupt-names: false
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else:
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required:
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- interrupts
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additionalProperties: false
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examples:
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@ -36,6 +36,12 @@ properties:
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minItems: 1
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maxItems: 2
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interrupts:
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maxItems: 1
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description: Pre-timeout interrupt from the watchdog.
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wakeup-source: true
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required:
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- compatible
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- reg
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|
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@ -953,6 +953,15 @@ config RENESAS_RZG2LWDT
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This driver adds watchdog support for the integrated watchdogs in the
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Renesas RZ/G2L SoCs. These watchdogs can be used to reset a system.
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config RENESAS_RZV2HWDT
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tristate "Renesas RZ/V2H(P) WDT Watchdog"
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depends on ARCH_R9A09G057 || COMPILE_TEST
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depends on PM || COMPILE_TEST
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select WATCHDOG_CORE
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help
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This driver adds watchdog support for the integrated watchdogs in the
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Renesas RZ/V2H(P) SoCs. These watchdogs can be used to reset a system.
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config ASPEED_WATCHDOG
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tristate "Aspeed BMC watchdog support"
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depends on ARCH_ASPEED || COMPILE_TEST
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@ -86,6 +86,7 @@ obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
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obj-$(CONFIG_RENESAS_RZAWDT) += rza_wdt.o
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obj-$(CONFIG_RENESAS_RZN1WDT) += rzn1_wdt.o
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obj-$(CONFIG_RENESAS_RZG2LWDT) += rzg2l_wdt.o
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obj-$(CONFIG_RENESAS_RZV2HWDT) += rzv2h_wdt.o
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obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
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obj-$(CONFIG_STM32_WATCHDOG) += stm32_iwdg.o
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obj-$(CONFIG_UNIPHIER_WATCHDOG) += uniphier_wdt.o
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@ -563,8 +563,8 @@ static int iTCO_wdt_probe(struct platform_device *pdev)
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}
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ident.firmware_version = p->iTCO_version;
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p->wddev.info = &ident,
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p->wddev.ops = &iTCO_wdt_ops,
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p->wddev.info = &ident;
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p->wddev.ops = &iTCO_wdt_ops;
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p->wddev.bootstatus = 0;
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p->wddev.timeout = WATCHDOG_TIMEOUT;
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watchdog_set_nowayout(&p->wddev, nowayout);
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@ -379,7 +379,7 @@ static void imx2_wdt_shutdown(struct platform_device *pdev)
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}
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/* Disable watchdog if it is active or non-active but still running */
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static int __maybe_unused imx2_wdt_suspend(struct device *dev)
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static int imx2_wdt_suspend(struct device *dev)
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{
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struct watchdog_device *wdog = dev_get_drvdata(dev);
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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@ -404,7 +404,7 @@ static int __maybe_unused imx2_wdt_suspend(struct device *dev)
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}
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/* Enable watchdog and configure it if necessary */
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static int __maybe_unused imx2_wdt_resume(struct device *dev)
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static int imx2_wdt_resume(struct device *dev)
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{
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struct watchdog_device *wdog = dev_get_drvdata(dev);
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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@ -435,8 +435,8 @@ static int __maybe_unused imx2_wdt_resume(struct device *dev)
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
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imx2_wdt_resume);
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static DEFINE_SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
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imx2_wdt_resume);
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static struct imx2_wdt_data imx_wdt = {
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.wdw_supported = true,
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@ -476,7 +476,7 @@ static struct platform_driver imx2_wdt_driver = {
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.shutdown = imx2_wdt_shutdown,
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.driver = {
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.name = DRIVER_NAME,
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.pm = &imx2_wdt_pm_ops,
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.pm = pm_sleep_ptr(&imx2_wdt_pm_ops),
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.of_match_table = imx2_wdt_dt_ids,
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},
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};
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@ -55,6 +55,7 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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struct imx_wdt_hw_feature {
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bool prescaler_enable;
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bool post_rcs_wait;
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u32 wdog_clock_rate;
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};
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@ -62,7 +63,6 @@ struct imx7ulp_wdt_device {
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struct watchdog_device wdd;
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void __iomem *base;
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struct clk *clk;
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bool post_rcs_wait;
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bool ext_reset;
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const struct imx_wdt_hw_feature *hw;
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};
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@ -95,7 +95,7 @@ static int imx7ulp_wdt_wait_rcs(struct imx7ulp_wdt_device *wdt)
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ret = -ETIMEDOUT;
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/* Wait 2.5 clocks after RCS done */
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if (wdt->post_rcs_wait)
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if (wdt->hw->post_rcs_wait)
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usleep_range(wait_min, wait_min + 2000);
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return ret;
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@ -334,15 +334,6 @@ static int imx7ulp_wdt_probe(struct platform_device *pdev)
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/* The WDOG may need to do external reset through dedicated pin */
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imx7ulp_wdt->ext_reset = of_property_read_bool(dev->of_node, "fsl,ext-reset-output");
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imx7ulp_wdt->post_rcs_wait = true;
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if (of_device_is_compatible(dev->of_node,
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"fsl,imx8ulp-wdt")) {
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dev_info(dev, "imx8ulp wdt probe\n");
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imx7ulp_wdt->post_rcs_wait = false;
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} else {
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dev_info(dev, "imx7ulp wdt probe\n");
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}
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wdog = &imx7ulp_wdt->wdd;
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wdog->info = &imx7ulp_wdt_info;
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wdog->ops = &imx7ulp_wdt_ops;
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@ -403,6 +394,12 @@ static const struct dev_pm_ops imx7ulp_wdt_pm_ops = {
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static const struct imx_wdt_hw_feature imx7ulp_wdt_hw = {
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.prescaler_enable = false,
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.wdog_clock_rate = 1000,
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.post_rcs_wait = true,
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};
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static const struct imx_wdt_hw_feature imx8ulp_wdt_hw = {
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.prescaler_enable = false,
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.wdog_clock_rate = 1000,
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};
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static const struct imx_wdt_hw_feature imx93_wdt_hw = {
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@ -411,8 +408,8 @@ static const struct imx_wdt_hw_feature imx93_wdt_hw = {
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};
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static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
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{ .compatible = "fsl,imx8ulp-wdt", .data = &imx7ulp_wdt_hw, },
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{ .compatible = "fsl,imx7ulp-wdt", .data = &imx7ulp_wdt_hw, },
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{ .compatible = "fsl,imx8ulp-wdt", .data = &imx8ulp_wdt_hw, },
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{ .compatible = "fsl,imx93-wdt", .data = &imx93_wdt_hw, },
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{ /* sentinel */ }
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};
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@ -56,6 +56,25 @@ static int imx_sc_wdt_ping(struct watchdog_device *wdog)
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return 0;
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}
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static bool imx_sc_wdt_is_running(void)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_START_WDOG,
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0, 0, 0, 0, 0, 0, &res);
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/* Already enabled (SC_TIMER_ERR_BUSY)? */
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if (res.a0 == SC_TIMER_ERR_BUSY)
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return true;
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/* Undo only if that was us who has (successfully) enabled the WDT */
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if (!res.a0)
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arm_smccc_smc(IMX_SIP_TIMER, IMX_SIP_TIMER_STOP_WDOG,
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0, 0, 0, 0, 0, 0, &res);
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return false;
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}
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static int imx_sc_wdt_start(struct watchdog_device *wdog)
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{
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struct arm_smccc_res res;
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@ -183,6 +202,9 @@ static int imx_sc_wdt_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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if (imx_sc_wdt_is_running())
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set_bit(WDOG_HW_RUNNING, &wdog->status);
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watchdog_stop_on_reboot(wdog);
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watchdog_stop_on_unregister(wdog);
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@ -216,29 +238,6 @@ register_device:
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return devm_watchdog_register_device(dev, wdog);
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}
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static int __maybe_unused imx_sc_wdt_suspend(struct device *dev)
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{
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struct imx_sc_wdt_device *imx_sc_wdd = dev_get_drvdata(dev);
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if (watchdog_active(&imx_sc_wdd->wdd))
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imx_sc_wdt_stop(&imx_sc_wdd->wdd);
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return 0;
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}
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static int __maybe_unused imx_sc_wdt_resume(struct device *dev)
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{
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struct imx_sc_wdt_device *imx_sc_wdd = dev_get_drvdata(dev);
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if (watchdog_active(&imx_sc_wdd->wdd))
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imx_sc_wdt_start(&imx_sc_wdd->wdd);
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(imx_sc_wdt_pm_ops,
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imx_sc_wdt_suspend, imx_sc_wdt_resume);
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static const struct of_device_id imx_sc_wdt_dt_ids[] = {
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{ .compatible = "fsl,imx-sc-wdt", },
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{ /* sentinel */ }
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|
|
@ -250,7 +249,6 @@ static struct platform_driver imx_sc_wdt_driver = {
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.driver = {
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.name = "imx-sc-wdt",
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.of_match_table = imx_sc_wdt_dt_ids,
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.pm = &imx_sc_wdt_pm_ops,
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},
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};
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module_platform_driver(imx_sc_wdt_driver);
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|
|
|
|||
|
|
@ -285,8 +285,8 @@ static int gti_wdt_probe(struct platform_device *pdev)
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}
|
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wdog_dev = &priv->wdev;
|
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wdog_dev->info = >i_wdt_ident,
|
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wdog_dev->ops = >i_wdt_ops,
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wdog_dev->info = >i_wdt_ident;
|
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wdog_dev->ops = >i_wdt_ops;
|
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wdog_dev->parent = dev;
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/*
|
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* Watchdog counter is 24 bit where lower 8 bits are zeros
|
||||
|
|
|
|||
|
|
@ -218,7 +218,7 @@ static int pm8916_wdt_probe(struct platform_device *pdev)
|
|||
return err;
|
||||
}
|
||||
|
||||
wdt->wdev.ops = &pm8916_wdt_ops,
|
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wdt->wdev.ops = &pm8916_wdt_ops;
|
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wdt->wdev.parent = dev;
|
||||
wdt->wdev.min_timeout = PM8916_WDT_MIN_TIMEOUT;
|
||||
wdt->wdev.max_timeout = PM8916_WDT_MAX_TIMEOUT;
|
||||
|
|
|
|||
273
drivers/watchdog/rzv2h_wdt.c
Normal file
273
drivers/watchdog/rzv2h_wdt.c
Normal file
|
|
@ -0,0 +1,273 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Renesas RZ/V2H(P) WDT Watchdog Driver
|
||||
*
|
||||
* Copyright (C) 2024 Renesas Electronics Corporation.
|
||||
*/
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/reset.h>
|
||||
#include <linux/units.h>
|
||||
#include <linux/watchdog.h>
|
||||
|
||||
#define WDTRR 0x00 /* WDT Refresh Register RW, 8 */
|
||||
#define WDTCR 0x02 /* WDT Control Register RW, 16 */
|
||||
#define WDTSR 0x04 /* WDT Status Register RW, 16 */
|
||||
#define WDTRCR 0x06 /* WDT Reset Control Register RW, 8 */
|
||||
|
||||
#define WDTCR_TOPS_1024 0x00
|
||||
#define WDTCR_TOPS_16384 0x03
|
||||
|
||||
#define WDTCR_CKS_CLK_1 0x00
|
||||
#define WDTCR_CKS_CLK_256 0x50
|
||||
|
||||
#define WDTCR_RPES_0 0x300
|
||||
#define WDTCR_RPES_75 0x000
|
||||
|
||||
#define WDTCR_RPSS_25 0x00
|
||||
#define WDTCR_RPSS_100 0x3000
|
||||
|
||||
#define WDTRCR_RSTIRQS BIT(7)
|
||||
|
||||
#define MAX_TIMEOUT_CYCLES 16384
|
||||
#define CLOCK_DIV_BY_256 256
|
||||
|
||||
#define WDT_DEFAULT_TIMEOUT 60U
|
||||
|
||||
static bool nowayout = WATCHDOG_NOWAYOUT;
|
||||
module_param(nowayout, bool, 0);
|
||||
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
|
||||
__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
|
||||
|
||||
struct rzv2h_wdt_priv {
|
||||
void __iomem *base;
|
||||
struct clk *pclk;
|
||||
struct clk *oscclk;
|
||||
struct reset_control *rstc;
|
||||
struct watchdog_device wdev;
|
||||
};
|
||||
|
||||
static int rzv2h_wdt_ping(struct watchdog_device *wdev)
|
||||
{
|
||||
struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
|
||||
|
||||
/*
|
||||
* The down-counter is refreshed and starts counting operation on
|
||||
* a write of the values 00h and FFh to the WDTRR register.
|
||||
*/
|
||||
writeb(0x0, priv->base + WDTRR);
|
||||
writeb(0xFF, priv->base + WDTRR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rzv2h_wdt_setup(struct watchdog_device *wdev, u16 wdtcr)
|
||||
{
|
||||
struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
|
||||
|
||||
/* Configure the timeout, clock division ratio, and window start and end positions. */
|
||||
writew(wdtcr, priv->base + WDTCR);
|
||||
|
||||
/* Enable interrupt output to the ICU. */
|
||||
writeb(0, priv->base + WDTRCR);
|
||||
|
||||
/* Clear underflow flag and refresh error flag. */
|
||||
writew(0, priv->base + WDTSR);
|
||||
}
|
||||
|
||||
static int rzv2h_wdt_start(struct watchdog_device *wdev)
|
||||
{
|
||||
struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
|
||||
int ret;
|
||||
|
||||
ret = pm_runtime_resume_and_get(wdev->parent);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = reset_control_deassert(priv->rstc);
|
||||
if (ret) {
|
||||
pm_runtime_put(wdev->parent);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* delay to handle clock halt after de-assert operation */
|
||||
udelay(3);
|
||||
|
||||
/*
|
||||
* WDTCR
|
||||
* - CKS[7:4] - Clock Division Ratio Select - 0101b: oscclk/256
|
||||
* - RPSS[13:12] - Window Start Position Select - 11b: 100%
|
||||
* - RPES[9:8] - Window End Position Select - 11b: 0%
|
||||
* - TOPS[1:0] - Timeout Period Select - 11b: 16384 cycles (3FFFh)
|
||||
*/
|
||||
rzv2h_wdt_setup(wdev, WDTCR_CKS_CLK_256 | WDTCR_RPSS_100 |
|
||||
WDTCR_RPES_0 | WDTCR_TOPS_16384);
|
||||
|
||||
/*
|
||||
* Down counting starts after writing the sequence 00h -> FFh to the
|
||||
* WDTRR register. Hence, call the ping operation after loading the counter.
|
||||
*/
|
||||
rzv2h_wdt_ping(wdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2h_wdt_stop(struct watchdog_device *wdev)
|
||||
{
|
||||
struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
|
||||
int ret;
|
||||
|
||||
ret = reset_control_assert(priv->rstc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = pm_runtime_put(wdev->parent);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct watchdog_info rzv2h_wdt_ident = {
|
||||
.options = WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT,
|
||||
.identity = "Renesas RZ/V2H WDT Watchdog",
|
||||
};
|
||||
|
||||
static int rzv2h_wdt_restart(struct watchdog_device *wdev,
|
||||
unsigned long action, void *data)
|
||||
{
|
||||
struct rzv2h_wdt_priv *priv = watchdog_get_drvdata(wdev);
|
||||
int ret;
|
||||
|
||||
if (!watchdog_active(wdev)) {
|
||||
ret = clk_enable(priv->pclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_enable(priv->oscclk);
|
||||
if (ret) {
|
||||
clk_disable(priv->pclk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(priv->rstc);
|
||||
if (ret) {
|
||||
clk_disable(priv->oscclk);
|
||||
clk_disable(priv->pclk);
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* Writing to the WDT Control Register (WDTCR) or WDT Reset
|
||||
* Control Register (WDTRCR) is possible once between the
|
||||
* release from the reset state and the first refresh operation.
|
||||
* Therefore, issue a reset if the watchdog is active.
|
||||
*/
|
||||
ret = reset_control_reset(priv->rstc);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* delay to handle clock halt after de-assert operation */
|
||||
udelay(3);
|
||||
|
||||
/*
|
||||
* WDTCR
|
||||
* - CKS[7:4] - Clock Division Ratio Select - 0000b: oscclk/1
|
||||
* - RPSS[13:12] - Window Start Position Select - 00b: 25%
|
||||
* - RPES[9:8] - Window End Position Select - 00b: 75%
|
||||
* - TOPS[1:0] - Timeout Period Select - 00b: 1024 cycles (03FFh)
|
||||
*/
|
||||
rzv2h_wdt_setup(wdev, WDTCR_CKS_CLK_1 | WDTCR_RPSS_25 |
|
||||
WDTCR_RPES_75 | WDTCR_TOPS_1024);
|
||||
|
||||
rzv2h_wdt_ping(wdev);
|
||||
|
||||
/* wait for underflow to trigger... */
|
||||
udelay(5);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct watchdog_ops rzv2h_wdt_ops = {
|
||||
.owner = THIS_MODULE,
|
||||
.start = rzv2h_wdt_start,
|
||||
.stop = rzv2h_wdt_stop,
|
||||
.ping = rzv2h_wdt_ping,
|
||||
.restart = rzv2h_wdt_restart,
|
||||
};
|
||||
|
||||
static int rzv2h_wdt_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rzv2h_wdt_priv *priv;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
priv->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(priv->base))
|
||||
return PTR_ERR(priv->base);
|
||||
|
||||
priv->pclk = devm_clk_get_prepared(&pdev->dev, "pclk");
|
||||
if (IS_ERR(priv->pclk))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), "no pclk");
|
||||
|
||||
priv->oscclk = devm_clk_get_prepared(&pdev->dev, "oscclk");
|
||||
if (IS_ERR(priv->oscclk))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(priv->oscclk), "no oscclk");
|
||||
|
||||
priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
|
||||
if (IS_ERR(priv->rstc))
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(priv->rstc),
|
||||
"failed to get cpg reset");
|
||||
|
||||
priv->wdev.max_hw_heartbeat_ms = (MILLI * MAX_TIMEOUT_CYCLES * CLOCK_DIV_BY_256) /
|
||||
clk_get_rate(priv->oscclk);
|
||||
dev_dbg(dev, "max hw timeout of %dms\n", priv->wdev.max_hw_heartbeat_ms);
|
||||
|
||||
ret = devm_pm_runtime_enable(&pdev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->wdev.min_timeout = 1;
|
||||
priv->wdev.timeout = WDT_DEFAULT_TIMEOUT;
|
||||
priv->wdev.info = &rzv2h_wdt_ident;
|
||||
priv->wdev.ops = &rzv2h_wdt_ops;
|
||||
priv->wdev.parent = dev;
|
||||
watchdog_set_drvdata(&priv->wdev, priv);
|
||||
watchdog_set_nowayout(&priv->wdev, nowayout);
|
||||
watchdog_stop_on_unregister(&priv->wdev);
|
||||
|
||||
ret = watchdog_init_timeout(&priv->wdev, 0, dev);
|
||||
if (ret)
|
||||
dev_warn(dev, "Specified timeout invalid, using default");
|
||||
|
||||
return devm_watchdog_register_device(&pdev->dev, &priv->wdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id rzv2h_wdt_ids[] = {
|
||||
{ .compatible = "renesas,r9a09g057-wdt", },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rzv2h_wdt_ids);
|
||||
|
||||
static struct platform_driver rzv2h_wdt_driver = {
|
||||
.driver = {
|
||||
.name = "rzv2h_wdt",
|
||||
.of_match_table = rzv2h_wdt_ids,
|
||||
},
|
||||
.probe = rzv2h_wdt_probe,
|
||||
};
|
||||
module_platform_driver(rzv2h_wdt_driver);
|
||||
MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
|
||||
MODULE_DESCRIPTION("Renesas RZ/V2H(P) WDT Watchdog Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user