835a486cd9
All RISC-V platforms have a single HW IPI provided by the INTC local interrupt controller. The HW method to trigger INTC IPI can be through external irqchip (e.g. RISC-V AIA), through platform specific device (e.g. SiFive CLINT timer), or through firmware (e.g. SBI IPI call). To support multiple IPIs on RISC-V, add a generic IPI multiplexing mechanism which help us create multiple virtual IPIs using a single HW IPI. This generic IPI multiplexing is inspired by the Apple AIC irqchip driver and it is shared by various RISC-V irqchip drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Hector Martin <marcan@marcan.st> Tested-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230103141221.772261-4-apatel@ventanamicro.com
3.3 KiB
SPDX-License-Identifier: GPL-2.0-only
menu "IRQ subsystem"
Options selectable by the architecture code
Make sparse irq Kconfig switch below available
config MAY_HAVE_SPARSE_IRQ bool
Legacy support, required for itanic
config GENERIC_IRQ_LEGACY bool
Enable the generic irq autoprobe mechanism
config GENERIC_IRQ_PROBE bool
Use the generic /proc/interrupts implementation
config GENERIC_IRQ_SHOW bool
Print level/edge extra information
config GENERIC_IRQ_SHOW_LEVEL bool
Supports effective affinity mask
config GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMP bool
Support for delayed migration from interrupt context
config GENERIC_PENDING_IRQ bool
Support for generic irq migrating off cpu before the cpu is offline.
config GENERIC_IRQ_MIGRATION bool
Alpha specific irq affinity mechanism
config AUTO_IRQ_AFFINITY bool
Interrupt injection mechanism
config GENERIC_IRQ_INJECTION bool
Tasklet based software resend for pending interrupts on enable_irq()
config HARDIRQS_SW_RESEND bool
Edge style eoi based handler (cell)
config IRQ_EDGE_EOI_HANDLER bool
Generic configurable interrupt chip implementation
config GENERIC_IRQ_CHIP bool select IRQ_DOMAIN
Generic irq_domain hw <--> linux irq number translation
config IRQ_DOMAIN bool
Support for simulated interrupts
config IRQ_SIM bool select IRQ_WORK select IRQ_DOMAIN
Support for hierarchical irq domains
config IRQ_DOMAIN_HIERARCHY bool select IRQ_DOMAIN
Support for obsolete non-mapping irq domains
config IRQ_DOMAIN_NOMAP bool select IRQ_DOMAIN
Support for hierarchical fasteoi+edge and fasteoi+level handlers
config IRQ_FASTEOI_HIERARCHY_HANDLERS bool
Generic IRQ IPI support
config GENERIC_IRQ_IPI bool depends on SMP select IRQ_DOMAIN_HIERARCHY
Generic IRQ IPI Mux support
config GENERIC_IRQ_IPI_MUX bool depends on SMP
Generic MSI hierarchical interrupt domain support
config GENERIC_MSI_IRQ bool select IRQ_DOMAIN_HIERARCHY
config IRQ_MSI_IOMMU bool
config IRQ_TIMINGS bool
config GENERIC_IRQ_MATRIX_ALLOCATOR bool
config GENERIC_IRQ_RESERVATION_MODE bool
Support forced irq threading
config IRQ_FORCED_THREADING bool
config SPARSE_IRQ bool "Support sparse irq numbering" if MAY_HAVE_SPARSE_IRQ help
Sparse irq numbering is useful for distro kernels that want
to define a high CONFIG_NR_CPUS value but still want to have
low kernel memory footprint on smaller machines.
( Sparse irqs can also be beneficial on NUMA boxes, as they spread
out the interrupt descriptors in a more NUMA-friendly way. )
If you don't know what to do here, say N.
config GENERIC_IRQ_DEBUGFS bool "Expose irq internals in debugfs" depends on DEBUG_FS select GENERIC_IRQ_INJECTION default n help
Exposes internal state information through debugfs. Mostly for
developers and debugging of hard to diagnose interrupt problems.
If you don't know what to do here, say N.
endmenu
config GENERIC_IRQ_MULTI_HANDLER bool help Allow to specify the low level IRQ handler at run time.
Cavium Octeon is the last system to use this deprecated option
Do not even think of enabling this on any new platform
config DEPRECATED_IRQ_CPU_ONOFFLINE bool depends on CAVIUM_OCTEON_SOC default CAVIUM_OCTEON_SOC