linux-fslc-qoriq: add lx2160acex7 support

Add support for Solid-Runs LX2160A based COM Express Type 7 Module and
machines built upon that module (see
https://www.solid-run.com/nxp-lx2160a-family/).

Signed-off-by: Jens Rehsack <sno@netbsd.org>
This commit is contained in:
Jens Rehsack 2020-06-11 18:09:03 +02:00 committed by Otavio Salvador
parent 0997a74f95
commit bd0f35ad04
7 changed files with 423 additions and 0 deletions

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From 0038ae610ef69f00adf358d915ae618a83ac63cb Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 4 May 2020 17:33:28 +0300
Subject: [PATCH] arm64: dts: lx2160a: add lx2160acex7 device tree build
Upstream-Status: Inappropriate [Solid-Run BSP]
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 5e05e0be3aeb..7d342cffb87e 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-cex7.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191.dtb \
imx8mm-ddr4-evk.dtb imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb \
--
2.17.1

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From 35dc5b03bb8f7b93fb474c39d7689d39062ff81a Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 28 Jul 2019 14:21:06 +0300
Subject: [PATCH 2/3] arm64: dts: lx2160a: add lx2160acex7 device tree
The device tree enables the following features -
1. dpmac17 RGMII MAC connected to Atheros AR8035 phy
2. 2x MDIO busses
3. 2x USB 3.0 controllers
4. 4x SATA ports
5. MT35X 512Mb SPI flash
6. Temperature sensor on i2c0 channel 3
7. AMC6821 temperature and PWM fan controller
The module supports AMC6821 and EMC2301 PWM controllers where either can
be assembled, but not both together since the PWM and TACH signals are
shared between them.
Upstream-Status: Inappropriate [Solid-Run BSP]
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
.../boot/dts/freescale/fsl-lx2160a-cex7.dts | 190 ++++++++++++++++++
1 file changed, 190 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
new file mode 100644
index 000000000000..872fcf9e724d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160A-CEx7
+//
+// Copyright 2019 SolidRun ltd.
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+ model = "SolidRun LX2160A COM express type 7 module";
+ compatible = "fsl,lx2160a-cex7", "fsl,lx2160a";
+
+ aliases {
+ crypto = &crypto;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ sb_3v3: regulator-sb3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "RT7290";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&esdhc0 {
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ status = "okay";
+};
+
+&esdhc1 {
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+ status = "okay";
+};
+
+
+/*
+i2c busses are -
+/dev/i2c0 - CTRL #0 - connected to PCA9547 I2C switch
+/dev/i2c1 - CTRL #2 - COM module to carrier (general I2C_CK/I2C_DAT)
+/dev/i2c2 - CTRL #4 - Connected to RTC PCF2129AT (0x51), EEPROM (0x54,0x55,0x56,0x57)
+
+I2C switch -
+/dev/i2c3 - CH0 - SO-DIMMs SPD (0x51, 0x53), 2Kb EEPROM (0x57), bootable 512Kb eeprom (0x50)
+/dev/i2c4 - CH1 - 100MHz clk gen (address 0x6a)
+/dev/i2c5 - CH2 - LTC3882 DC-DC controller on 0x63
+/dev/i2c6 - CH3 - SA56004ED (0x4c), SA56004FD (0x4d), COM module SMB_CK,SMB_DAT and COM module 10G_LED_SDA,10G_LED_SCL
+/dev/i2c7 - CH4 - SFP #0 I2C
+/dev/i2c8 - CH5 - SFP #1 I2C
+/dev/i2c9 - CH6 - SFP #2 I2C
+/dev/i2c10 - CH7 - SFP #3 I2C
+
+
+*/
+
+
+
+&i2c0 {
+ status = "okay";
+
+ i2c-mux@77 {
+ compatible = "nxp,pca9547";
+ reg = <0x77>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ fan-temperature-ctrlr@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+
+ temperature-sensor@48 {
+ compatible = "nxp,sa56004";
+ reg = <0x48>;
+ vcc-supply = <&sb_3v3>;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ // IRQ10_B
+ interrupts = <0 150 0x4>;
+ };
+};
+
+&fspi {
+ status = "okay";
+ flash0: mt35xu512aba@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "micron,m25p80";
+ m25p,fast-read;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&usb1 {
+ status = "okay";
+};
+
+&emdio1 {
+ status = "okay";
+ rgmii_phy1: ethernet-phy@1 {
+ /* AR8035 PHY - "compatible" property not strictly needed */
+ compatible = "ethernet-phy-id004d.d072";
+ reg = <0x1>;
+ /* Poll mode - no "interrupts" property defined */
+ };
+};
+
+&emdio2 {
+ status = "okay";
+};
+
+&dpmac17 {
+ phy-handle = <&rgmii_phy1>;
+ phy-connection-type = "rgmii-id";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sata1 {
+ status = "okay";
+};
+
+&sata2 {
+ status = "okay";
+};
+
+&sata3 {
+ status = "okay";
+};
--
2.17.1

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From cca2439ac83136b9ed85f8519931018d4f5385e6 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 12 Jan 2020 14:24:47 +0200
Subject: [PATCH] arm64: dts: lx2160a-cex7: add ltc3882 support
ltc3882 is lx2 cortex-a72 core voltage.
this patch adds it to the device tree support; the driver is in
drivers/hwmon/pmbus/ltc2978.c
Upstream-Status: Inappropriate [Solid-Run BSP]
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
index 872fcf9e724d..1c1a0d47897d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
@@ -94,6 +94,15 @@ I2C switch -
#cooling-cells = <2>;
};
};
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ ltc3882@5c {
+ compatible = "ltc3882";
+ reg = <0x5c>;
+ };
+ };
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1

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@ -0,0 +1,54 @@
From 05acb6ecc8eb7426c4664a1e8fd22ad69256d541 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Sun, 26 Jan 2020 15:36:07 +0200
Subject: [PATCH] arm64: dts: lx2160a-cex7: add on-module eeproms
This patch adds 4 eeprom support on i2c mux channel #0 -
1. Bootable 512Kbit eeprom at address 0x50.
2. Memory SO-DIMMs SPD channels at 0x51 (upper SO-DIMM) and 0x53.
3. 2Kb eeprom at 0x57 will be used by SolidRun to hold manufacturing
data.
Upstream-Status: Inappropriate [Solid-Run BSP]
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
.../boot/dts/freescale/fsl-lx2160a-cex7.dts | 22 ++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
index 1c1a0d47897d..2b8f1118b37a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
@@ -81,7 +81,27 @@ I2C switch -
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
-
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0>;
+ 24aa512@50 {
+ compatible = "atmel,24c512";
+ reg = <0x50>;
+ };
+ spd1@51 {
+ compatible = "atmel,spd";
+ reg = <0x51>;
+ };
+ spd2@53 {
+ compatible = "atmel,spd";
+ reg = <0x53>;
+ };
+ m24c02@57 {
+ compatible = "atmel,24c02";
+ reg = <0x57>;
+ };
+ };
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1

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From 927a01dffed9eb439bc9bf6df0b6548380bc84a7 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Mon, 10 Feb 2020 10:47:45 +0200
Subject: [PATCH] pci: hotplug: declare IDT bridge as hotpluggabl bridge
Upstream-Status: Inappropriate [Solid-Run BSP]
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
drivers/pci/quirks.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 55870dd42b4d..bfac025931e0 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2915,6 +2915,7 @@ static void quirk_hotplug_bridge(struct pci_dev *dev)
dev->is_hotplug_bridge = 1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IDT, 0x808c, quirk_hotplug_bridge);
/*
* This is a quirk for the Ricoh MMC controller found as a part of some
--
2.17.1

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From bba6ebb2daac17bd2268c97b7255e477c2b15b52 Mon Sep 17 00:00:00 2001
From: Rabeeh Khoury <rabeeh@solid-run.com>
Date: Wed, 26 Feb 2020 17:57:54 +0200
Subject: [PATCH] pci: spr2803: quirk to fix class ID
spr2803 class is 0x0, this quirk modifies that to multimedia class in
order to allocate memory to it's bars.
Upstream-Status: Inappropriate [Solid-Run BSP]
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
---
drivers/pci/quirks.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 28c64f84bfe7..4ddf7e43d531 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3068,6 +3068,18 @@ static void fixup_ti816x_class(struct pci_dev *dev)
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
+static void fixup_spr2803_class(struct pci_dev *dev)
+{
+ u32 class = dev->class;
+
+ /* spr2803 does not have class code */
+ dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
+ pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
+ class, dev->class);
+}
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x1e00, 0x2803,
+ PCI_CLASS_NOT_DEFINED, 8, fixup_spr2803_class);
+
/*
* Some PCIe devices do not work reliably with the claimed maximum
* payload size supported.
--
2.17.1

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FILESEXTRAPATHS_append_lx2160acex7 := "${THISDIR}/${PN}-lx2160acex7:"
SRC_URI_append_lx2160acex7 = "\
file://0001-arm64-dts-lx2160a-add-lx2160acex7-device-tree-build.patch \
file://0002-arm64-dts-lx2160a-add-lx2160acex7-device-tree.patch \
file://0005-arm64-dts-lx2160a-cex7-add-ltc3882-support.patch \
file://0006-arm64-dts-lx2160a-cex7-add-on-module-eeproms.patch \
file://0007-pci-hotplug-declare-IDT-bridge-as-hotpluggabl-bridge.patch \
file://0008-pci-spr2803-quirk-to-fix-class-ID.patch \
"