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linux-fslc-qoriq: add lx2160acex7 support
Add support for Solid-Runs LX2160A based COM Express Type 7 Module and machines built upon that module (see https://www.solid-run.com/nxp-lx2160a-family/). Signed-off-by: Jens Rehsack <sno@netbsd.org>
This commit is contained in:
parent
0997a74f95
commit
bd0f35ad04
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@ -0,0 +1,27 @@
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From 0038ae610ef69f00adf358d915ae618a83ac63cb Mon Sep 17 00:00:00 2001
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From: Rabeeh Khoury <rabeeh@solid-run.com>
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Date: Mon, 4 May 2020 17:33:28 +0300
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Subject: [PATCH] arm64: dts: lx2160a: add lx2160acex7 device tree build
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Upstream-Status: Inappropriate [Solid-Run BSP]
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Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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---
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arch/arm64/boot/dts/freescale/Makefile | 1 +
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1 file changed, 1 insertion(+)
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diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
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index 5e05e0be3aeb..7d342cffb87e 100644
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--- a/arch/arm64/boot/dts/freescale/Makefile
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+++ b/arch/arm64/boot/dts/freescale/Makefile
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@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-cex7.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191.dtb \
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imx8mm-ddr4-evk.dtb imx8mm-evk-root.dtb imx8mm-evk-inmate.dtb \
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--
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2.17.1
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|
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@ -0,0 +1,225 @@
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From 35dc5b03bb8f7b93fb474c39d7689d39062ff81a Mon Sep 17 00:00:00 2001
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From: Rabeeh Khoury <rabeeh@solid-run.com>
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Date: Sun, 28 Jul 2019 14:21:06 +0300
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Subject: [PATCH 2/3] arm64: dts: lx2160a: add lx2160acex7 device tree
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The device tree enables the following features -
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1. dpmac17 RGMII MAC connected to Atheros AR8035 phy
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2. 2x MDIO busses
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3. 2x USB 3.0 controllers
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4. 4x SATA ports
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5. MT35X 512Mb SPI flash
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6. Temperature sensor on i2c0 channel 3
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7. AMC6821 temperature and PWM fan controller
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The module supports AMC6821 and EMC2301 PWM controllers where either can
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be assembled, but not both together since the PWM and TACH signals are
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shared between them.
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Upstream-Status: Inappropriate [Solid-Run BSP]
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Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
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---
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.../boot/dts/freescale/fsl-lx2160a-cex7.dts | 190 ++++++++++++++++++
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1 file changed, 190 insertions(+)
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create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
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diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
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new file mode 100644
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index 000000000000..872fcf9e724d
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--- /dev/null
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
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@@ -0,0 +1,190 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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+//
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+// Device Tree file for LX2160A-CEx7
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+//
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+// Copyright 2019 SolidRun ltd.
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+
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+/dts-v1/;
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+
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+#include "fsl-lx2160a.dtsi"
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+
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+/ {
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+ model = "SolidRun LX2160A COM express type 7 module";
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+ compatible = "fsl,lx2160a-cex7", "fsl,lx2160a";
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+
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+ aliases {
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+ crypto = &crypto;
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+ serial0 = &uart0;
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+ serial1 = &uart1;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ sb_3v3: regulator-sb3v3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "RT7290";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+};
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+
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+&crypto {
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+ status = "okay";
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+};
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+
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+&esdhc0 {
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+ sd-uhs-sdr104;
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+ sd-uhs-sdr50;
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+ sd-uhs-sdr25;
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+ sd-uhs-sdr12;
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+ status = "okay";
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+};
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+
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+&esdhc1 {
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+ mmc-hs200-1_8v;
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+ mmc-hs400-1_8v;
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+ bus-width = <8>;
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+ status = "okay";
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+};
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+
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+
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+/*
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+i2c busses are -
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+/dev/i2c0 - CTRL #0 - connected to PCA9547 I2C switch
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+/dev/i2c1 - CTRL #2 - COM module to carrier (general I2C_CK/I2C_DAT)
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+/dev/i2c2 - CTRL #4 - Connected to RTC PCF2129AT (0x51), EEPROM (0x54,0x55,0x56,0x57)
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+
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+I2C switch -
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+/dev/i2c3 - CH0 - SO-DIMMs SPD (0x51, 0x53), 2Kb EEPROM (0x57), bootable 512Kb eeprom (0x50)
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+/dev/i2c4 - CH1 - 100MHz clk gen (address 0x6a)
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+/dev/i2c5 - CH2 - LTC3882 DC-DC controller on 0x63
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+/dev/i2c6 - CH3 - SA56004ED (0x4c), SA56004FD (0x4d), COM module SMB_CK,SMB_DAT and COM module 10G_LED_SDA,10G_LED_SCL
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+/dev/i2c7 - CH4 - SFP #0 I2C
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+/dev/i2c8 - CH5 - SFP #1 I2C
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+/dev/i2c9 - CH6 - SFP #2 I2C
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+/dev/i2c10 - CH7 - SFP #3 I2C
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+
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+
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+*/
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+
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+
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+
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+&i2c0 {
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+ status = "okay";
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+
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+ i2c-mux@77 {
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+ compatible = "nxp,pca9547";
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+ reg = <0x77>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ i2c@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x1>;
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+ fan-temperature-ctrlr@18 {
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+ compatible = "ti,amc6821";
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+ reg = <0x18>;
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+ cooling-min-state = <0>;
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+ cooling-max-state = <9>;
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+ #cooling-cells = <2>;
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+ };
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+ };
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+ i2c@3 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x3>;
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+
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+ temperature-sensor@48 {
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+ compatible = "nxp,sa56004";
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+ reg = <0x48>;
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+ vcc-supply = <&sb_3v3>;
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+ };
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+ };
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+ };
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+};
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+
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+&i2c2 {
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+ status = "okay";
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+};
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+
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+&i2c4 {
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+ status = "okay";
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+
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+ rtc@51 {
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+ compatible = "nxp,pcf2129";
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+ reg = <0x51>;
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+ // IRQ10_B
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+ interrupts = <0 150 0x4>;
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+ };
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+};
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+
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+&fspi {
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+ status = "okay";
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+ flash0: mt35xu512aba@0 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "micron,m25p80";
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+ m25p,fast-read;
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+ spi-max-frequency = <50000000>;
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+ reg = <0>;
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+ /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
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+ spi-rx-bus-width = <8>;
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+ spi-tx-bus-width = <1>;
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+ };
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ status = "okay";
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+};
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+
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+&usb0 {
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+ status = "okay";
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+};
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+
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+&usb1 {
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+ status = "okay";
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+};
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+
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+&emdio1 {
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+ status = "okay";
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+ rgmii_phy1: ethernet-phy@1 {
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+ /* AR8035 PHY - "compatible" property not strictly needed */
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+ compatible = "ethernet-phy-id004d.d072";
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+ reg = <0x1>;
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+ /* Poll mode - no "interrupts" property defined */
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+ };
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+};
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+
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+&emdio2 {
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+ status = "okay";
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+};
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+
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+&dpmac17 {
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+ phy-handle = <&rgmii_phy1>;
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+ phy-connection-type = "rgmii-id";
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+};
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+
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+&sata0 {
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+ status = "okay";
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+};
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+
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+&sata1 {
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+ status = "okay";
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+};
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+
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+&sata2 {
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+ status = "okay";
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+};
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+
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+&sata3 {
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+ status = "okay";
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+};
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--
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2.17.1
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|
|
@ -0,0 +1,39 @@
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From cca2439ac83136b9ed85f8519931018d4f5385e6 Mon Sep 17 00:00:00 2001
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From: Rabeeh Khoury <rabeeh@solid-run.com>
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Date: Sun, 12 Jan 2020 14:24:47 +0200
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Subject: [PATCH] arm64: dts: lx2160a-cex7: add ltc3882 support
|
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ltc3882 is lx2 cortex-a72 core voltage.
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this patch adds it to the device tree support; the driver is in
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drivers/hwmon/pmbus/ltc2978.c
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|
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Upstream-Status: Inappropriate [Solid-Run BSP]
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|
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Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
|
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---
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arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts | 9 +++++++++
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1 file changed, 9 insertions(+)
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diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
|
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index 872fcf9e724d..1c1a0d47897d 100644
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--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
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+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
|
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@@ -94,6 +94,15 @@ I2C switch -
|
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#cooling-cells = <2>;
|
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};
|
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};
|
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+ i2c@2 {
|
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0x2>;
|
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+ ltc3882@5c {
|
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+ compatible = "ltc3882";
|
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+ reg = <0x5c>;
|
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+ };
|
||||
+ };
|
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i2c@3 {
|
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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--
|
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2.17.1
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
From 05acb6ecc8eb7426c4664a1e8fd22ad69256d541 Mon Sep 17 00:00:00 2001
|
||||
From: Rabeeh Khoury <rabeeh@solid-run.com>
|
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Date: Sun, 26 Jan 2020 15:36:07 +0200
|
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Subject: [PATCH] arm64: dts: lx2160a-cex7: add on-module eeproms
|
||||
|
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This patch adds 4 eeprom support on i2c mux channel #0 -
|
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1. Bootable 512Kbit eeprom at address 0x50.
|
||||
2. Memory SO-DIMMs SPD channels at 0x51 (upper SO-DIMM) and 0x53.
|
||||
3. 2Kb eeprom at 0x57 will be used by SolidRun to hold manufacturing
|
||||
data.
|
||||
|
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Upstream-Status: Inappropriate [Solid-Run BSP]
|
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|
||||
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
|
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---
|
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.../boot/dts/freescale/fsl-lx2160a-cex7.dts | 22 ++++++++++++++++++-
|
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1 file changed, 21 insertions(+), 1 deletion(-)
|
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|
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diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
|
||||
index 1c1a0d47897d..2b8f1118b37a 100644
|
||||
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
|
||||
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dts
|
||||
@@ -81,7 +81,27 @@ I2C switch -
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
-
|
||||
+ i2c@0 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ reg = <0x0>;
|
||||
+ 24aa512@50 {
|
||||
+ compatible = "atmel,24c512";
|
||||
+ reg = <0x50>;
|
||||
+ };
|
||||
+ spd1@51 {
|
||||
+ compatible = "atmel,spd";
|
||||
+ reg = <0x51>;
|
||||
+ };
|
||||
+ spd2@53 {
|
||||
+ compatible = "atmel,spd";
|
||||
+ reg = <0x53>;
|
||||
+ };
|
||||
+ m24c02@57 {
|
||||
+ compatible = "atmel,24c02";
|
||||
+ reg = <0x57>;
|
||||
+ };
|
||||
+ };
|
||||
i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
--
|
||||
2.17.1
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
From 927a01dffed9eb439bc9bf6df0b6548380bc84a7 Mon Sep 17 00:00:00 2001
|
||||
From: Rabeeh Khoury <rabeeh@solid-run.com>
|
||||
Date: Mon, 10 Feb 2020 10:47:45 +0200
|
||||
Subject: [PATCH] pci: hotplug: declare IDT bridge as hotpluggabl bridge
|
||||
|
||||
Upstream-Status: Inappropriate [Solid-Run BSP]
|
||||
|
||||
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
|
||||
---
|
||||
drivers/pci/quirks.c | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
|
||||
index 55870dd42b4d..bfac025931e0 100644
|
||||
--- a/drivers/pci/quirks.c
|
||||
+++ b/drivers/pci/quirks.c
|
||||
@@ -2915,6 +2915,7 @@ static void quirk_hotplug_bridge(struct pci_dev *dev)
|
||||
dev->is_hotplug_bridge = 1;
|
||||
}
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
|
||||
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IDT, 0x808c, quirk_hotplug_bridge);
|
||||
|
||||
/*
|
||||
* This is a quirk for the Ricoh MMC controller found as a part of some
|
||||
--
|
||||
2.17.1
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
From bba6ebb2daac17bd2268c97b7255e477c2b15b52 Mon Sep 17 00:00:00 2001
|
||||
From: Rabeeh Khoury <rabeeh@solid-run.com>
|
||||
Date: Wed, 26 Feb 2020 17:57:54 +0200
|
||||
Subject: [PATCH] pci: spr2803: quirk to fix class ID
|
||||
|
||||
spr2803 class is 0x0, this quirk modifies that to multimedia class in
|
||||
order to allocate memory to it's bars.
|
||||
|
||||
Upstream-Status: Inappropriate [Solid-Run BSP]
|
||||
|
||||
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
|
||||
---
|
||||
drivers/pci/quirks.c | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
|
||||
index 28c64f84bfe7..4ddf7e43d531 100644
|
||||
--- a/drivers/pci/quirks.c
|
||||
+++ b/drivers/pci/quirks.c
|
||||
@@ -3068,6 +3068,18 @@ static void fixup_ti816x_class(struct pci_dev *dev)
|
||||
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
|
||||
PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
|
||||
|
||||
+static void fixup_spr2803_class(struct pci_dev *dev)
|
||||
+{
|
||||
+ u32 class = dev->class;
|
||||
+
|
||||
+ /* spr2803 does not have class code */
|
||||
+ dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
|
||||
+ pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
|
||||
+ class, dev->class);
|
||||
+}
|
||||
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x1e00, 0x2803,
|
||||
+ PCI_CLASS_NOT_DEFINED, 8, fixup_spr2803_class);
|
||||
+
|
||||
/*
|
||||
* Some PCIe devices do not work reliably with the claimed maximum
|
||||
* payload size supported.
|
||||
--
|
||||
2.17.1
|
||||
|
10
recipes-kernel/linux/linux-fslc-qoriq_5.4.bbappend
Normal file
10
recipes-kernel/linux/linux-fslc-qoriq_5.4.bbappend
Normal file
|
@ -0,0 +1,10 @@
|
|||
FILESEXTRAPATHS_append_lx2160acex7 := "${THISDIR}/${PN}-lx2160acex7:"
|
||||
|
||||
SRC_URI_append_lx2160acex7 = "\
|
||||
file://0001-arm64-dts-lx2160a-add-lx2160acex7-device-tree-build.patch \
|
||||
file://0002-arm64-dts-lx2160a-add-lx2160acex7-device-tree.patch \
|
||||
file://0005-arm64-dts-lx2160a-cex7-add-ltc3882-support.patch \
|
||||
file://0006-arm64-dts-lx2160a-cex7-add-on-module-eeproms.patch \
|
||||
file://0007-pci-hotplug-declare-IDT-bridge-as-hotpluggabl-bridge.patch \
|
||||
file://0008-pci-spr2803-quirk-to-fix-class-ID.patch \
|
||||
"
|
Loading…
Reference in New Issue
Block a user