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riscv tunes: ISA Implementation of RISC-V tune features
This implements the following base ISAs: * rv32i, rv64i * rv32e, rv64i The following ABIs: * ilp32, ilp32e, ilp32f, ilp32d * lp64, lp64e, lp64f, lp64d The following ISA extension are also implemented: * M - Integer Multiplication and Division Extension * A - Atomic Memory Extension * F - Single-Precision Floating-Point Extension * D - Double-Precision Floating-Point Extension * C - Compressed Extension * B - Bit Manipulation Extension (implies Zba, Zbb, Zbs) * V - Vector Operations Extension * Zicsr - Control and Status Register Access Extension * Zifencei - Instruction-Fetch Fence Extension * Zba - Address bit manipulation extension * Zbb - Basic bit manipulation extension * Zbc - Carry-less multiplication extension * Zbs - Single-bit manipulation extension * Zicbom - Cache-block management extension The existing processors tunes are preserved: * riscv64 (rv64gc) * riscv32 (rv32gc) * riscv64nf (rv64imac_zicsr_zifencei) * riscv32nf (rv32imac_zicsr_zifencei) * riscv64nc (rv64imafd_zicsr_zifencei) Previously defined feature 'big-endian' has been removed as it was not used. (From OE-Core rev: bcaf298a146dfd10e4c8f44223ea083bc4baf45c) Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Richard Purdie <richard.purdie@linuxfoundation.org>
This commit is contained in:
Mark Hatle
Richard Purdie
parent
63fb85ec37
commit
3c5c4cfa6b
122
meta/conf/machine/include/riscv/README
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122
meta/conf/machine/include/riscv/README
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@ -0,0 +1,122 @@
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2025/06/08 - Mark Hatle <mark.hatle@amd.com>
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- Initial Revision
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The RISC-V ISA is broken into two parts, a base ISA and extensions. As
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of the writing of this document these are documented at:
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https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications
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Specifically "The RISC-V Instruction Set Manual Volume I: Unprivileged ISA"
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was used to create this implementation.
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Requirements
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------------
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As RISC-V is a “variable” ISA (a base isa plus numerous extensions), a
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mechanism is required to specify a series of ISA features that a user or
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tune can use to specify a specific CPU instantiation.
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Not all ratified or draft features should or can be implemented with the
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available resources.
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The implementation should work for Linux, baremetal (newlib), zephyr and
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other operating systems. Supported extensions should be based on
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real-world examples.
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Linux
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-----
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Linux required base and support extensions should be available. Linux
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requires:
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* Base: rv32ima & rv64ima
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* Optional FPU: fd
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* Optional RISCV_ISA_C: c
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* Optiona RISCV_ISA_V: v
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* Required additional: _zicsr_zifencei
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* Optional RISCV_ISA_ZBA: _zba
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* Optional RISCV_ISA_ZBB: _zbb
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* Optional RISCV_ISA_ZBC: _zbc (not supported by current QEMU design)
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See: https://git.yoctoproject.org/linux-yocto/tree/arch/riscv/Makefile?h=v6.12/base
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Baremetal
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---------
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AMD Microblaze-V FPGA support uses the following static configurations:
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Base: rv32e, rv32i, rv64i
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Extensions: m, a, f, d, c, b, zicsr, zifencei
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Zephyr
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------
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AMD Microblaze-V development for Zephyr is the same as Baremetal, with a
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few additional extensions: zbc, zicbom
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ABI
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---
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The following ABIs are supported GNU tools and some combination of systems.
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* ilp32 - Integer, long and pointer are 32-bit
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* lp64 - Long and pointer are 64-bit (integer is 32-bit)
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The ABI is dependent upon the core system implementation, as ilp32 can
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only used on an ‘rv32’ system, while lp64 can only be used on an ‘rv64’
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system.
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There are additional variations of each ABI:
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* e - used with the Reduced register extension
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* f - used when single precision floating point (but not double precision) is
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enabled
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* d - used when both single and double precision floating point is enabled
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Based on the above, the ABI should be automatically determined based on
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the selected Base ISA and Extensions.
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Implementation
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--------------
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To make it easier to generate the RISC-V canonical arch, ISA based -march,
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and the ABI string, a few new variables are added for specific RISC-V items.
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TUNE_RISCV_ARCH - This contains the canonical GNU style arch, generally this
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will evaluate to "riscv32" or "riscv64".
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TUNE_RISCV_MARCH - This will contain an ISA based -march string compatible
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with gcc and similar toolchains. For example:
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rv32imacfd_zicsr_zifencei
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TUNE_RISCV_ABI - This is the generated ABI that corresponds to the ARCH and
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MARCH/ISA values. For riscv32, the value will be ilp32
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(int, long and pointer is 32-bit) with the ISA
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variation. For riscv64, the value will be lp64 (long
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and pointer are 64-bit bit, while int is 32-bit) with the
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ISA variation. The ISA affects the ABI when the 'e', 'f'
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and 'd' extension are used.
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TUNE_RISCV_PKGARCH - This is the generated PKGARCH value.
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The standard variables are defined as:
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TUNE_CCARGS = "${@ '-march=${TUNE_RISCV_MARCH} -mabi=${TUNE_RISCV_ABI}' if not d.getVar('TUNE_CCARGS:tune-${DEFAULTTUNE}') else 'TUNE_CCARGS:tune-${DEFAULTTUNE}'}"
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The above will allow the user to specify an implementation specific
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TUNE_CCARGS for a given processor tune if the default implementtion is
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not adequate for some reason. It is expected that most, if not all,
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implementations will use the default behavior.
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TUNE_ARCH = "${TUNE_RISCV_ARCH}"
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TUNE_PKGARCH = "${TUNE_RISCV_PKGARCH}"
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The above two will always base their setting off the standard TUNE_FEATURES.
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Ratified and draft extensions should be implemented as TUNE_FEATURES in
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the arch-riscv.inc file.
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Vendor specific extensions and processor specific settings should go
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into a 'tune-<vendor>.inc' file, with tune-riscv.inc being reserved for
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general purpose tunes.
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TUNE_FEATURE Helper
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-------------------
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A special helper function has been written that will convert RISC-V ISA
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notation into TUNE_FEATURE notion, for example:
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rv32g -> rv 32 i m a f d zicsr zifencei
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The helper can be called using oe.tune.riscv_isa_to_tune("<ISA>") such as
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oe.tune.riscv_isa_to_tune("rv64gc") which would return:
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rv 64 i m a f d c zicsr zifencei
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@ -1,14 +1,140 @@
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# RISCV Architecture definition
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DEFAULTTUNE ?= "riscv64"
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# Based on the RISC-V Instruction Set Manual Volume I: Unprivileged ISA from May 2025
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# As well as the RISC-V options for using GCC (as of June 2025)
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TUNE_ARCH = "${TUNE_ARCH:tune-${DEFAULTTUNE}}"
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TUNE_PKGARCH = "${TUNE_PKGARCH:tune-${DEFAULTTUNE}}"
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TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nf', ' -mabi=lp64', ' ', d)}"
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TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv32nf', ' -mabi=ilp32', ' ', d)}"
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# Note: the following should be implemented in the order that GCC expects
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# -march= values to be defined in.
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TUNE_CCARGS:append = "${@bb.utils.contains('TUNE_FEATURES', 'riscv64nc', ' -march=rv64imafd', ' ', d)}"
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# Base ISA
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# All supported march strings must start with rv32 or rv64
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TUNEVALID[rv] = "RISC-V"
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TUNE_RISCV_ARCH = "${@bb.utils.contains("TUNE_FEATURES", "rv", "riscv", "", d)}"
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TUNE_RISCV_MARCH = "${@bb.utils.contains("TUNE_FEATURES", "rv", "rv", "", d)}"
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TUNE_RISCV_ABI = ""
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# There are two primary ABIs, ilp32 and lp64
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# There are variants of both, that appears to be based on extensions above
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# For example:
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# rv32i uses ilp32, rv32e uses ilp32e, rv32f uses ilp32f
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# rv64i uses lp64, rv64if uses lp64f, rv64id uses lp64d
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TUNEVALID[32] = "ISA XLEN - 32-bit"
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TUNECONFLICTS[32] = "64"
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TUNE_RISCV_ARCH .= "${@bb.utils.contains("TUNE_FEATURES", "32", "32", "", d)}"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "32", "32", "", d)}"
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TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "32", "ilp32", "", d)}"
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TUNEVALID[64] = "ISA XLEN - 64-bit"
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TUNECONFLICTS[64] = "32"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "64", "64", "", d)}"
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TUNE_RISCV_ARCH .= "${@bb.utils.contains("TUNE_FEATURES", "64", "64", "", d)}"
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TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "64", "lp64", "", d)}"
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# The package arch starts with the canonical arch, but adds some extensions to make
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# package compatibility clear
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TUNE_RISCV_PKGARCH = "${TUNE_RISCV_ARCH}"
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# i, e, or g are defined by gcc, but 'g' refers to 'i' + extensions 'MAFD Zicsr Zifencei'
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# So 'g' will not be defined here as it is an abbreviation of the expanded version
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TUNEVALID[e] = "Reduced register base integer extension"
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TUNECONFLICTS[e] = "i"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}"
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TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "e", "e", "", d)}"
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TUNEVALID[i] = "Base integer extension"
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TUNECONFLICTS[i] = "e"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "i", "i", "", d)}"
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# Extensions
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TUNEVALID[m] = "Integer multiplication and division extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "m", "m", "", d)}"
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TUNEVALID[a] = "Atomic extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "a", "a", "", d)}"
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TUNEVALID[f] = "Single-precision floating-point extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "f d", "f", "", d)}"
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TUNEVALID[d] = "Double-precision floating-point extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", "", d)}"
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# Only f OR d, but just one
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TUNE_RISCV_ABI .= "${@bb.utils.contains("TUNE_FEATURES", "d", "d", bb.utils.contains("TUNE_FEATURES", "f", "f", "", d), d)}"
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TUNEVALID[c] = "Compressed extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "c", "c", "", d)}"
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TUNEVALID[b] = "Bit Manipulation extension"
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# Handled below via zba, zbb, zbs
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# This matches current Linux kernel behavior
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#TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}"
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#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "b", "b", "", d)}"
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TUNEVALID[v] = "Vector operations extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "v", "v", "", d)}"
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# Now the special Z extensions
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TUNEVALID[zicbom] = "Cache-block management extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicbom", "_zicbom", "", d)}"
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TUNEVALID[zicsr] = "Control and status register access extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
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# If zicsr (or zifencei) is in the path, OpenSBI fails to use the extensions, do to (Makefile):
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# # Check whether the assembler and the compiler support the Zicsr and Zifencei extensions
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# CC_SUPPORT_ZICSR_ZIFENCEI := $(shell $(CC) $(CLANG_TARGET) $(RELAX_FLAG) -nostdlib -march=rv$(OPENSBI_CC_XLEN)imafd_zicsr_zifencei -x c /dev/null -o /dev/null 2>&1 | grep -e "zicsr" -e "zifencei" > /dev/null && echo n || echo y)
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# this will match on the path containing zicsr or zifencei when an error is reported, which
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# will always happens in this check.
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#
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# Yocto Project Bugzilla 15897
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#
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#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zicsr f d", "_zicsr", "", d)}"
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TUNEVALID[zifencei] = "Instruction-fetch fence extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
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# See above Bug 15897
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#TUNE_RISCV_PKGARCH .= "${@bb.utils.contains("TUNE_FEATURES", "zifencei", "_zifencei", "", d)}"
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TUNEVALID[zba] = "Address bit manipulation extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zba", "_zba", "", d)}"
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TUNEVALID[zbb] = "Basic bit manipulation extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbb", "_zbb", "", d)}"
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TUNEVALID[zbc] = "Carry-less multiplication extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "zbc", "_zbc", "", d)}"
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TUNEVALID[zbs] = "Single-bit manipulation extension"
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TUNE_RISCV_MARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}"
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TUNE_RISCV_PKGARCH .= "${@bb.utils.contains_any("TUNE_FEATURES", "b zbs", "_zbs", "", d)}"
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# Construct TUNE_CCARGS
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# This should result in a CCARG similar to:
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# -march=rv32imac -mabi=ilp32
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TUNE_CCARGS = "${@ '-march=${TUNE_RISCV_MARCH} -mabi=${TUNE_RISCV_ABI}' if not d.getVar('TUNE_CCARGS:tune-${DEFAULTTUNE}') else 'TUNE_CCARGS:tune-${DEFAULTTUNE}'}"
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# Construct TUNE_ARCH
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# This should result in an arch string similar to:
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# riscv32
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TUNE_ARCH = "${TUNE_RISCV_ARCH}"
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# Construct TUNE_PKGARCH
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# This should result in a package are like:
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# riscv32imac
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TUNE_PKGARCH = "${TUNE_RISCV_PKGARCH}"
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# Misc settings
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# Fix: ld: unrecognized option '--hash-style=sysv'
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LINKER_HASH_STYLE:libc-newlib = ""
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LINKER_HASH_STYLE:libc-picolibc = ""
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@ -1,41 +1,23 @@
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require conf/machine/include/riscv/arch-riscv.inc
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TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
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TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
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TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
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TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
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TUNEVALID[riscv64nc] = "Enable 64-bit RISC-V optimizations without compressed instructions"
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TUNEVALID[bigendian] = "Big endian mode"
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DEFAULTTUNE ?= "riscv64"
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AVAILTUNES += "riscv64 riscv32 riscv64nc riscv64nf riscv32nf"
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# Default
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TUNE_FEATURES:tune-riscv64 = "riscv64"
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TUNE_ARCH:tune-riscv64 = "riscv64"
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TUNE_PKGARCH:tune-riscv64 = "riscv64"
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PACKAGE_EXTRA_ARCHS:tune-riscv64 = "riscv64"
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TUNE_FEATURES:tune-riscv64 := "${@oe.tune.riscv_isa_to_tune("rv64gc")}"
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PACKAGE_EXTRA_ARCHS:tune-riscv64 = "${TUNE_RISCV_PKGARCH}"
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TUNE_FEATURES:tune-riscv32 = "riscv32"
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TUNE_ARCH:tune-riscv32 = "riscv32"
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TUNE_PKGARCH:tune-riscv32 = "riscv32"
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PACKAGE_EXTRA_ARCHS:tune-riscv32 = "riscv32"
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TUNE_FEATURES:tune-riscv32 := "${@oe.tune.riscv_isa_to_tune("rv32gc")}"
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PACKAGE_EXTRA_ARCHS:tune-riscv32 = "${TUNE_RISCV_PKGARCH}"
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# No float
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TUNE_FEATURES:tune-riscv64nf = "${TUNE_FEATURES:tune-riscv64} riscv64nf"
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TUNE_ARCH:tune-riscv64nf = "riscv64"
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TUNE_PKGARCH:tune-riscv64nf = "riscv64nf"
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PACKAGE_EXTRA_ARCHS:tune-riscv64nf = "riscv64nf"
|
||||
TUNE_FEATURES:tune-riscv64nf := "${@oe.tune.riscv_isa_to_tune("rv64imac_zicsr_zifencei")}"
|
||||
PACKAGE_EXTRA_ARCHS:tune-riscv64nf = "${TUNE_RISCV_PKGARCH}"
|
||||
|
||||
TUNE_FEATURES:tune-riscv32nf = "${TUNE_FEATURES:tune-riscv32} riscv32nf"
|
||||
TUNE_ARCH:tune-riscv32nf = "riscv32"
|
||||
TUNE_PKGARCH:tune-riscv32nf = "riscv32nf"
|
||||
PACKAGE_EXTRA_ARCHS:tune-riscv32nf = "riscv32nf"
|
||||
TUNE_FEATURES:tune-riscv32nf := "${@oe.tune.riscv_isa_to_tune("rv32imac_zicsr_zifencei")}"
|
||||
PACKAGE_EXTRA_ARCHS:tune-riscv32nf = "${TUNE_RISCV_PKGARCH}"
|
||||
|
||||
# no compressed
|
||||
TUNE_FEATURES:tune-riscv64nc = "${TUNE_FEATURES:tune-riscv64} riscv64nc"
|
||||
TUNE_ARCH:tune-riscv64nc = "riscv64"
|
||||
TUNE_PKGARCH:tune-riscv64nc = "riscv64nc"
|
||||
PACKAGE_EXTRA_ARCHS:tune-riscv64nc = "riscv64nc"
|
||||
TUNE_FEATURES:tune-riscv64nc := "${@oe.tune.riscv_isa_to_tune("rv64imafd_zicsr_zifencei")}"
|
||||
PACKAGE_EXTRA_ARCHS:tune-riscv64nc = "${TUNE_RISCV_PKGARCH}"
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
#@NAME: generic riscv32 machine
|
||||
#@DESCRIPTION: Machine configuration for running a generic riscv32
|
||||
|
||||
require conf/machine/include/riscv/qemuriscv.inc
|
||||
DEFAULTTUNE ?= "riscv32"
|
||||
|
||||
DEFAULTTUNE = "riscv32"
|
||||
require conf/machine/include/riscv/qemuriscv.inc
|
||||
|
||||
PREFERRED_VERSION_openocd-native = "riscv"
|
||||
PREFERRED_VERSION_openocd = "riscv"
|
||||
|
|
|
|||
|
|
@ -12,4 +12,4 @@ __path__ = extend_path(__path__, __name__)
|
|||
BBIMPORTS = ["qa", "data", "path", "utils", "types", "package", "packagedata", \
|
||||
"packagegroup", "sstatesig", "lsb", "cachedpath", "license", "qemu", \
|
||||
"reproducible", "rust", "buildcfg", "go", "spdx30_tasks", "spdx_common", \
|
||||
"cve_check"]
|
||||
"cve_check", "tune"]
|
||||
|
|
|
|||
81
meta/lib/oe/tune.py
Normal file
81
meta/lib/oe/tune.py
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
#
|
||||
# Copyright OpenEmbedded Contributors
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
#
|
||||
|
||||
# riscv_isa_to_tune(isa)
|
||||
#
|
||||
# Automatically translate a RISC-V ISA string to TUNE_FEATURES
|
||||
#
|
||||
# Abbreviations, such as rv32g -> rv32imaffd_zicsr_zifencei are supported.
|
||||
#
|
||||
# Profiles, such as rva22u64, are NOT supported, you must use ISA strings.
|
||||
#
|
||||
def riscv_isa_to_tune(isa):
|
||||
_isa = isa.lower()
|
||||
|
||||
feature = []
|
||||
iter = 0
|
||||
|
||||
# rv or riscv
|
||||
if _isa[iter:].startswith('rv'):
|
||||
feature.append('rv')
|
||||
iter = iter + 2
|
||||
elif _isa[iter:].startswith('riscv'):
|
||||
feature.append('rv')
|
||||
iter = iter + 5
|
||||
else:
|
||||
# Not a risc-v ISA!
|
||||
return _isa
|
||||
|
||||
while (_isa[iter:]):
|
||||
# Skip _ and whitespace
|
||||
if _isa[iter] == '_' or _isa[iter].isspace():
|
||||
iter = iter + 1
|
||||
continue
|
||||
|
||||
# Length, just capture numbers here
|
||||
if _isa[iter].isdigit():
|
||||
iter_end = iter
|
||||
while iter_end < len(_isa) and _isa[iter_end].isdigit():
|
||||
iter_end = iter_end + 1
|
||||
|
||||
feature.append(_isa[iter:iter_end])
|
||||
iter = iter_end
|
||||
continue
|
||||
|
||||
# Typically i, e or g is next, followed by extensions.
|
||||
# Extensions are single character, except for Z, Ss, Sh, Sm, Sv, and X
|
||||
|
||||
# If the extension starts with 'Z', 'S' or 'X' use the name until the next _, whitespace or end
|
||||
if _isa[iter] in ['z', 's', 'x']:
|
||||
ext_type = _isa[iter]
|
||||
iter_end = iter + 1
|
||||
|
||||
# Multicharacter extension, these are supposed to have a _ before the next multicharacter extension
|
||||
# See 37.4 and 37.5:
|
||||
# 37.4: Underscores "_" may be used to separate ISA extensions...
|
||||
# 37.5: All multi-letter extensions ... must be separated from other multi-letter extensions by an underscore...
|
||||
# Some extensions permit only alphabetic characters, while others allow alphanumeric chartacters
|
||||
while iter_end < len(_isa) and _isa[iter_end] != "_" and not _isa[iter_end].isspace():
|
||||
iter_end = iter_end + 1
|
||||
|
||||
feature.append(_isa[iter:iter_end])
|
||||
iter = iter_end
|
||||
continue
|
||||
|
||||
# 'g' is special, it's an abbreviation for imafd_zicsr_zifencei
|
||||
# When expanding the abbreviation, any additional letters must appear before the _z* extensions
|
||||
if _isa[iter] == 'g':
|
||||
_isa = 'imafd' + _isa[iter+1:] + '_zicsr_zifencei'
|
||||
iter = 0
|
||||
continue
|
||||
|
||||
feature.append(_isa[iter])
|
||||
iter = iter + 1
|
||||
continue
|
||||
|
||||
# Eliminate duplicates, but preserve the order
|
||||
feature = list(dict.fromkeys(feature))
|
||||
return ' '.join(feature)
|
||||
Loading…
Reference in New Issue
Block a user