Debugging feature to enable time synchronised logging of:
- the Message exchange over MU with FW.
- IOCTL(s)
- any user articulated debug messages.
The logs are saved to a file in the linux filesystem.
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Acked-by: Rahul Kumar Yadav <rahulkumar.yadav@nxp.com>
Acked-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Acked-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
additional changes to the upstream driver.
- construct se_name from se_type_id and instance id
- move soc_register to info_list
- move fetch soc info function pointer to info_list
- ele soc fetch generalization
- ele debug dump
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Acked-by: Rahul Kumar Yadav <rahulkumar.yadav@nxp.com>
Acked-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Acked-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
NXP hardware IP(s) for secure-enclaves like Edgelock Enclave(ELE),
are embedded in the SoC to support the features like HSM, SHE & V2X,
using message based communication interface.
The secure enclave FW communicates on a dedicated messaging unit(MU)
based interface(s) with application core, where kernel is running.
It exists on specific i.MX processors. e.g. i.MX8ULP, i.MX93.
This patch adds the driver for communication interface to secure-enclave,
for exchanging messages with NXP secure enclave HW IP(s) like EdgeLock
Enclave (ELE) from Kernel-space, used by kernel management layers like
- DM-Crypt.
squash e7d2fac2d1ceb TBS: LF-14067: drivers: firmware: imx: se suspend-resume
squash c4c9b2f7cf710 TBS: drivers: firmware: imx: correct macro ELE_DEBUG_DUMP_RSP_SZ value
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Acked-by: Rahul Kumar Yadav <rahulkumar.yadav@nxp.com>
Acked-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Acked-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Gaurav Jain <gaurav.jain@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
When not getting the se-fw2 device, calling read_common_fuse() or
ele_write_fuse() will result in segmentation fault because fuse->se_dev
is a NULL pointer. Check fuse->se_dev to avoid this error.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
This update is according to i.MX95_Fusemap_v1.13_documentation.
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Design team says that the frequency limitation mentioned at controller
specification is just a general guideline for the IP. The maximum frequency
depends on the process technology and SoC architecture requirement of the
SoC. Specifically for i.MX95, the frequency of dspx_clk is signed off at
350MHz at UD/NM/OD mode. So 350MHz is the limit of the chip, not 300MHz.
So, change maximum FrameGen display clock frequency from 300MHz to 350MHz.
Reported-by: Qiang Li <qiang.li@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Add some USB3 PHY tuning properties for imx95-15x15-evk and
imx95-19x19-evk boards.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Fix USB3 PHY tuning properties name and parameters value.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
The i.MX8MP and i.MX95 USB3 PHY have different tuning parameter for same
tuning field, this will add i.MX95 tuning support.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
The description of TX_VBOOST_LVL is wrong in register PHY_CTRL3
bit[31:29].
The updated description as below:
011: Corresponds to a launch amplitude of 0.844 V.
100: Corresponds to a launch amplitude of 1.008 V.
101: Corresponds to a launch amplitude of 1.156 V.
This will fix the parsing function
phy_tx_vboost_level_from_property() to return correct value.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
The parameter value of below 3 properties are USB PHY specific. i.MX8MP
and i.MX95 USB PHY has different meanings. This will enlarge parameters
value and add constraints for them.
- fsl,phy-tx-vref-tune-percent
- fsl,phy-tx-rise-tune-percent
- fsl,phy-comp-dis-tune-percent
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
The ticket TKT0676370 shows the description of TX_VBOOST_LVL is wrong
in register PHY_CTRL3 bit[31:29].
011: Corresponds to a launch amplitude of 1.12 V.
010: Corresponds to a launch amplitude of 1.04 V.
000: Corresponds to a launch amplitude of 0.88 V.
After updated:
011: Corresponds to a launch amplitude of 0.844 V.
100: Corresponds to a launch amplitude of 1.008 V.
101: Corresponds to a launch amplitude of 1.156 V.
This will correct it accordingly.
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Jun Li <jun.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
The usb phy in i.MX95 is compatible with i.MX8MP's, this will add a
compatible "fsl,imx95-usb-phy" for i.MX95. Also change reg maxItems
to 2 since i.MX95 needs another regmap to control Type-C Assist (TCA)
block. Since i.MX95 usb phy is able to switch SS lanes, this will also
add orientation-switch and port property to the file.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Link: https://lore.kernel.org/r/20240911061720.495606-1-xu.yang_2@nxp.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Applications may set data_offset when it refers to an output queue. So
driver need to account for it when getting the start address of input
image in the plane.
Meanwhile data_offset is included in bytesused. So the data_offset
should be subtracted from the payload of input image.
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
same as LF-11706 in lf-6.12.y, remove blk_ctrl register for gpu
Signed-off-by: Jiyu Yang <jiyu.yang@nxp.com>
Reviewed-by: Xianzhong Li <xianzhong.li@nxp.com>
Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
same as LF-11706 in lf-6.12.y, need use the latest SM dev branch
Signed-off-by: Jiyu Yang <jiyu.yang@nxp.com>
Reviewed-by: Xianzhong Li <xianzhong.li@nxp.com>
Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
same as LF-11706 in lf-6.12.y, add directive for the gpumix reset control,
which has been moved into SM.
Change-Id: Ide9d01e34cd6b9061d177f70c6caacb785732f22
Signed-off-by: Jiyu Yang <jiyu.yang@nxp.com>
Signed-off-by: Jessie Hao <juan.hao@nxp.com>
Reviewed-by: Xianzhong Li <xianzhong.li@nxp.com>
Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Page flip is done usually with DRM vblank event. To ensure the page flip
case works efficiently, move queueing state event prior to waiting for
ExtDst SHDLD done instead of the other way around so that DRM vblank event
can be handled in vblank IRQ handler as soon as possible because this
enables DisEngCFG frame complete IRQ(vblank IRQ) early enough. Note that
DisEngCFG frame complete IRQ comes after ExtDst SHDLD IRQ comes about a
time duration of an entire vblank, so timing is critical if the vblank time
duration is short. A problematic case caused by missing the critical
timing is that low page flip frame rate is seen on i.MX95 B0 EVK with
RM692C9 MIPI DSI panel.
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Now that VScaler4 issue in i.MX95 A0/A1 SoC is fixed in i.MX95 B0 SoC, use
soc_device_match() to figure out the i.MX95 SoC revision and enable VScaler4
support only for B0. Only add scaling support for VScaler4 in KMS because
it's not clear how to support de-interlacing. While at it, initialize
VScaler9 as a blit engine component in the DPU95 core driver.
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Add scaling filter property for plane so that users may choose to use
DRM_SCALING_FILTER_DEFAULT or DRM_SCALING_FILTER_NEAREST_NEIGHBOR
filters. By default, use DRM_SCALING_FILTER_DEFAULT(linear) filter.
Suggested-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Add SMMU support for NETC of i.MX95 B0.
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Clark Wang <xiaoning.wang@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Update the settings in imx95-19x19-evk-tja1103-rmii.dts to support it
only on i.MX95 B0 chip.
- enetc0 can be enabled at the same time
- ENETREF will always use 250MHz
- only need one ref clock pad
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
When USB3.0 host controller send data to OUT endpoint of USB device,
the data may be corrupted on USB bus if the controller send more than
4 1024 byte packets in one data burst transfer. This can be workaround
by changing the max burst size for tx transfer. According to the testing,
set max burst size to 4 can work fine for both U-disk and USB SSD devices.
This patch will also set snps,tx-thr-num-pkt to 1, although this property
doesn't have impact on the performance, but it's needed to make
snps,tx-max-burst take effect.
To limit tx maxburst on i.MX95 A1, this will call soc_device_match() to
match A1 chip.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
This reverts commit 010d4e215d.
Since i.MX95 B0 has fixed this IP issue. So remove this workaround now.
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
use GPU_CGC(174) to manage the GPU clock source since i.MX95 B0
Signed-off-by: Jiyu Yang <jiyu.yang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
fix potential compiler issue on many platforms:
error: macro "__assign_str" passed 2 arguments, but takes just 1
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
The wave6 decoder support identical size ranges horizontally as
vertically.
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Signed-off-by: Ming Zhou <ming.zhou@nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
When colorspace change, but size is not changed, firmware still trigger
a source chagne event.
1. Implement decoder start cmd.
2. Report V4L2_EVENT_SRC_CH_COLORSPACE if only colorspace change
3. Don't do buffer allocation again if only colorspace change
4. Use macro to magic number 32
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
If colorspace changes, the client needs to renegotiate the pipeline,
otherwise the decoded frame may not be displayed correctly.
When a colorspace change in the stream, the decoder sends a
V4L2_EVENT_SOURCE_CHANGE event with changes set to
V4L2_EVENT_SRC_CH_COLORSPACE. After client receive this source change
event, then client can switch to the correct stream setting. And each
frame can be displayed properly.
So add colorspace as a trigger parameter for dynamic resolution change.
Signed-off-by: Ming Qian <ming.qian@oss.nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Add a new source change V4L2_EVENT_SRC_CH_COLORSPACE that
indicates colorspace change in the stream.
The change V4L2_EVENT_SRC_CH_RESOLUTION will always affect
the allocation, but V4L2_EVENT_SRC_CH_COLORSPACE won't.
Signed-off-by: Ming Qian <ming.qian@oss.nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Firmware may require work buffer in handling create_instance,
that dma_alloc_coherent with GFP_KERNEL may spend too much
time, that may led to CREATE_INSTANCE timeout, then fail the
pipeline.
So just preallocate some work buffers, to reduce the probability of
timeout
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Make delay interval in read_poll_timeout, take the initiative to
yield the scheduling.
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Reviewed-by: Zhou Peng <eagle.zhou@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
update wave6 v4l2 driver to v1.3.11,
and fix the following issues:
1. NXPSEU-377: solve encoder rc issue
2. reduce the required sram size from 96K to 82K
and retain the following changes:
1. fix compile errors
2. LF-11686-9: mxc: vpu: wave6: report the firmware git sha code
3. LF-10942-1: mxc: vpu: wave6: add a debugfs to get the firmware log
4. LF-10942-2: mxc: vpu: wave6: support to reload firmware
5. LF-13605: sync bounce buffer
6. LF-13681: arm64: virtio video: adjust 6.12 version
7. increase some error log levels
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
Signed-off-by: Ming Qian <ming.qian@nxp.com>
Signed-off-by: TaoJiang <tao.jiang_2@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Because soc device is not ready when sysctr probes, so directly use
smccc to get soc version. For i.MX95 B0, no need to quirk to workaround
the system counter issue.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Add iommus property for SDHC
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Read the temperature returns "Resource temporarily unavailable" when
it's below 0 degree. Because the register DATA0 is a 16-bit signed value,
but the origin code converted directly unsigned 32-bit into a signed
32-bit value.
This patch adds a new 16-bit signed variable and uses readw to replace
readl.
Signed-off-by: Yanan Yang <yanan.yang@nxp.com>
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
The continuous mode has been deleted form imx91 RM, so change
the driver use mode.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Fix NULL pointer access occurring when the 'netc-interfaces' property
is missing or not properly defined in DTS. The parsing function,
netc_prb_parse_if, expects to find "netc-interfaces" property
definition to allocate memory for pi->ifmode array.
Signed-off-by: Florin Leotescu <florin.leotescu@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Only a block size of 4 bytes is supported, so divide the offset by 4 to obtain
the correct word count, as is done in other drivers such as: imx-ocotp.c
How to reproduce the bug?
e.g. try to write first word of the MAC_ADDR1 on imx93
FUSE_DEV=/sys/bus/nvmem/devices/fsb_s400_fuse0/nvmem
OFFSET_MAC=315
dd if=<binfile> of=$FUSE_DEV bs=4 count=1 seek=$OFFSET_MAC conv=notrunc
fsl-se-fw se-fw2: Command Id[214], Status=0x29, Indicator=0xA7
ELE_WRONG_SIZE_FAILURE_IND:0xA7, because the fuse being programmed
is not in the SoC fuse map.
Signed-off-by: Michael Glembotzki <Michael.Glembotzki@iris-sensing.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
The previouse PME_TURN_OFF kick off method on i.MX95 is wrong.
The PME_TURN_OFF_REQ (BIT19 of PE0_TX_MSG_REQ) should be toggled to
issue PME_TURN_OFF message on i.MX95.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Tested-by: Sherry Sun <sherry.sun@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Regmap cache mechanism is enabled in default. Thus, IO expander wouldn't
handle GPIO set really before resuming back.
But there are cases need to toggle gpio in NO_IRQ stage.
e.g. To align with PCIe specification, PERST# signal connected on the IO
expander must be toggled during PCIe RC's NO_IRQ_RESUME.
Do not enable the regmap cache when IO expander doesn't have the regulator
during system PM. That means the power of IO expander would be kept on,
and the GPIOs of the IO expander can be toggled really during system PM.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Reviewed-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Sherry Sun <sherry.sun@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Correct typo for pad macro name of ENET1_TD3 and I2C2_SCL.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
When using a cmdline such as "bportals=s0 qportals=s0", Linux is given a
single QMan and a single BMan portal which is shared among all CPUs, and
accessed with locking.
This is only supported for the staging SDK QBMan driver and not for the
upstream variant.
In a strange twist of events, qman_create_affine_slave() also sets
affine_portals[] for CPUs which use the portal affine to a different CPU
(aka "slaves" here), and just have portal->sharing_redirect set to that
other portal.
But that panics the kernel hard, because these dummy portals, not
having been created by qman_create_portal(), have uninitialized struct
qm_portal :: addr, eqcr, dqrr, etc, but also portal->config. So any time
these are dereferenced, the kernel panics.
There are actually 2 code paths which are in this situation:
qman_enable_irqs()
-> qm_isr_status_clear()
-> __qm_isr_write()
-> __qm_out(&portal->addr, ...) // portal->addr uninitialized
qm_shutdown_fq()
-> qm_get_portal_for_channel()
-> qman_p_get_portal_config()
-> &p->config->public_cfg // p->config uninitialized
Both functions were actually copied over from the upstream QBMan driver
(for the purpose of kexec support), which does not support portal
sharing and thus the problem does not exist there.
Actually, we need to take into consideration in these code paths only
those affine portals created by qman_create_affine_portal(), and not the
fake ones with sharing_redirect. The qman_create_affine_portal() sets
the CPU in the &affine_mask retrievable through qman_affine_cpus().
This is also the way in which dpaa_eth_add_channel() from
drivers/net/ethernet/freescale/sdk_dpaa/dpaa_eth_common.c avoids the
fake channels, when dereferencing the affine_cpus[] array through the
qman_get_affine_portal() API method.
Fixes: a218c908c8 ("staging: fsl_qbman: account for pre-initialized BARs in case of kexec")
Fixes: 78ff3aa0713b ("staging: fsl_qbman: use correct portal for static dequeues in qm_shutdown_fq()")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
neutron requires more memory to support large size firmware, merge
dtcm and dtcm-ring buffer for larger contiguous memory.
Signed-off-by: Jiwei.Fu <jiwei.fu@nxp.com>
Reviewed-by: Forrest Shi <xuelin.shi@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Jason Liu <jason.hui.liu@nxp.com>
